2022年QFN封装设计 .pdf

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1、Footprint Design and Surface Mount Application for QFN/ DFN Package App Note QA200501-A 1 1. Introduction 立理, QFN/ DFN Package (Quad Flat No-lead, Dual Flat No-lead)中央有一個大面積的散熱片(SMD). QFN Package (面)/ DFN Package ( 矩形面)良導功性功能量, (Figure 1)QFN 的封装和 CSP(Chip Scale Package), QFN, 與 PCB(Print Circuit Boa

2、rd)的電性和機械連接是通過QFN 四周底部的焊盤 (Pad)與 PCB 焊盤 (Footprint or Land Pattern) 上印刷錫膏、過 IR 回焊流来實現的 , SMT(Surface Mount Technology)有關於 PCB Footprint 設計 , 目前業界參考 IPC-SM-782, 但是 QFN 对 PCB 焊盤設計仍然是屬於較新的製程, 相關的 QFN Footprint 設計規格仍在發展中 , 所以此份 Application Note 提供使用者有關於QFN General Guideline。數, Guideline, 理, Figure 1: QF

3、N Section View 2. QFN/ DFN Outline Drawings有關於 RichTek QFN/ DFN Package Outline 請參考 RichTek Data Sheet Outline Dimension, 亦可在 RichTek Web-site4.1.2 Outline DimensionPackageOutline Dimension. 3. SMT ProcessSMT 數良率, 數SMT參Factors Control Point Solder Paste Shippment and Storeage Tempture, Paste Expirat

4、ion Date, Viscosity and Texture, Dry out, Stencil Design PCB Quality Clean, Flat, Residue, Wrapage Reflow Profile Profile Depended PCB Design, PCB Thickness, Compontent Placement SMT Machine, Orientation, Speed, Alignment Mark 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - -

5、 - - 第 1 页，共 6 页 - - - - - - - - - Footprint Design and Surface Mount Application for QFN/ DFN Package App Note QA200501-A 2 4. Stencil Design Guideline4.1 度Stencil Thickness Design , 列: 雷, 金. 度, 略Footprint, 1:1Footprint. IPC-7525. 130um150um(56mils), 150um易連度(更不), 參數4.2 Stencil Design for Thermal P

6、ad 了Package QFNPCBThermal Pad, Thermal Pad , Thermal Pad易洞 Void, Splatter, Solder Balling, 易(Fig2), Thermal Pad率50%80%, 連40%列, 列65 um(5065um Depend on PCB 力) PCB(Fig.3) Non-wetting toTerminalMoldingCompoundFig.2 Excess Exposed Pad SolderPCBThermal PadThermal PadStencil OpeningPCB SolderMask Opening6

7、5um*4 SideFig. 3: Thermal Pad Stencil Design名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 2 页，共 6 页 - - - - - - - - - Footprint Design and Surface Mount Application for QFN/ DFN Package App Note QA200501-A 3 4.3 Terminal Lead Stencil Design Solder(Lead)50um75um 立度(S

8、tand-off), 兩: Area Ratio: Area of Aperture open/ Aperture Wall Area=LW/2T(L+W) ? Area Ratio 0.66 Aspect Ratio: Aperture With/ Stencil Thickness= W/T ? Aspect Ratio 1.5 L: Aperture Length; W: Aperture Width; T: Stencil Thickness 5. PCB Footprint Guideline5.1 Footprint Drawing Table 1: Typical Footpri

9、nt Dimension X: Pad Width+0.05mm; Y: Pad Length+0.20mm; ZD Max: D+ PKG Tolerance+2(0.2); GD Min: D-2(Lmax)-2(0.05); D2th: GDmin-2(CpL=0.2) & Thermal Pad Open, 兩Package (mm) PCB Footprint Dimension Body Lead Pad Width Pad Length Pitch ZD MaxGD Min ZE MaxGE Min D2th E2th X Y DFN 2*2 6 0.30 0.40 0.65 2

10、.50 1.10 0.70 1.40 0.35 0.60 DFN 2*2 8 0.30 0.40 0.50 2.50 1.10 0.60 1.20 0.35 0.60 DFN 3*3 6 0.45 0.525 0.95 3.50 1.85 1.45 2.30 0.50 0.725 DFN 3*3 8 0.30 0.525 0.65 3.50 1.85 1.45 2.30 0.35 0.725 DFN 3*3 10 0.30 0.45 0.50 3.50 2.00 1.60 2.50 0.35 0.65 QFN 3*3 16 0.30 0.45 0.50 3.50 2.00 3.50 2.00

11、1.60 1.60 0.35 0.65 QFN 4*4 16 0.35 0.60 0.65 4.50 2.70 4.50 2.70 2.25 2.25 0.40 0.80 QFN 4*4 24 0.30 0.45 0.50 4.50 3.00 4.50 3.00 2.60 2.60 0.35 0.65 QFN 5*5 16 0.35 0.60 0.80 5.50 3.70 5.50 3.70 3.25 3.25 0.40 0.80 QFN 5*5 24 0.35 0.45 0.65 5.50 4.00 5.50 4.00 3.25 3.25 0.40 0.65 QFN 5*5 32 0.30

12、0.45 0.50 5.50 4.00 5.50 4.00 3.60 3.60 0.35 0.65 QFN 6*6 28 0.375 0.45 0.65 6.50 5.00 6.50 5.00 4.225 4.225 0.425 0.65 QFN 6*6 40 0.30 0.45 0.50 6.50 5.00 6.50 5.00 4.40 4.40 0.35 0.65 Fig. 4: Typical QFN/ DFN FootprintDesign with PackageQ FNP adP CB FootprintYXPitchD2thZE M axZD M axE2thGD M in0.1

13、5mmM ain G apG E M in00.15 mm名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 3 页，共 6 页 - - - - - - - - - Footprint Design and Surface Mount Application for QFN/ DFN Package App Note QA200501-A 4 5.2 Solder Mask Design PCB了, PCB(Solder Mask), , 若, , (Solder Mask Define

14、: SMD). 若, , (Non-solder Mask Defined)(Fig.5) LeadNon-Solder Mask Defined, 來Thermal PadSolder Mask Defined, 來5.3 Thermal Pad Via Design 了PCB金, , Thermal Pad. 參: 1.2mm Pitch with Via Diameter of 0.34mm(/ 料Solder Wicking, 0.25mm(0.010”) via, 例0.34mm1略0.25mm洞)(Fig. 6) DeviceDeviceFig. 5 Comparison betw

15、een Solder Mask Defined Pad and Non-solder Mask Defined PadSolder MaskSubstratePadSolder Mask DefinedNon-solder Mask Defined2*2 Body3*3 Body4*4 Body5*5 Body6*6 Body1.2 mm Via Pitch0.34 mm Via DiameterFig. 6 Suggested Thermal Via Layout名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 -

16、 - - - - - - 第 4 页，共 6 页 - - - - - - - - - Footprint Design and Surface Mount Application for QFN/ DFN Package App Note QA200501-A 5 SMT連洞ViaSolder Wicking, Thermal Pad行類塞, 塞: PCB爐, 路留爐, 路防止表面錫膏流入孔內造成虛焊影響黏貼列塞來Solder Wicking: Capped Via (Copper Layer Cover Via & Plugged Material) Plugged Via (Solder

17、Mask Cover Via & Plugged Material) Tented Via (Solder Mask Cover Via) 6. Re-flow Profile All of RichTeks products are requested to meet the standard of Reflow Profile in the IPC/JEDEC J-STD-020C. (Fig.8) Solder MaskCopperCapped ViaPlugged MaterialPlugged ViaTented ViaFig. 7 Via Type名师资料总结 - - -精品资料欢

18、迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 5 页，共 6 页 - - - - - - - - - Footprint Design and Surface Mount Application for QFN/ DFN Package App Note QA200501-A 6 7.0 Rework Process PCB?PCB?IC? IR Re-flow ?Fig.8 IR-Re-flow Profile 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 6 页，共 6 页 - - - - - - - - -