2022年VHDL编写IIC程序 .pdf

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1、如题所示，本文是使用VHDL语言编写的IIC 总线的 24C02 的读写例程，程序加了中文注释便于想我一样的初学者理解，写使用的写一个字节，读使用的随机读，具体参考 24c02 的手册library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity iic_com is port( clk: in STD_LOGIC; rst_n: in STD_LOGIC; sw1_en: in STD_LOGIC; - 读使能sw2_en: in

2、STD_LOGIC; - 写使能scl: out STD_LOGIC; sda: inout STD_LOGIC; dis_data: out STD_LOGIC_VECTOR (7 downto 0) ); end entity iic_com; architecture iic_communication of iic_com is signal sw_state: STD_LOGIC; signal cnt_delay: STD_LOGIC_VECTOR (8 downto 0); signal scl_pos: STD_LOGIC; signal scl_hig: STD_LOGIC;

3、 signal scl_neg: STD_LOGIC; signal scl_low: STD_LOGIC; signal db_r: STD_LOGIC_VECTOR (7 downto 0); signal read_data: STD_LOGIC_VECTOR (7 downto 0); signal sda_r: STD_LOGIC; signal sda_in: STD_LOGIC; signal sda_link: STD_LOGIC; signal num: STD_LOGIC_VECTOR (3 downto 0); constant DEVICE_READ: STD_LOGI

4、C_VECTOR (7 downto 0) := 10100001;-器件地址读constant DEVICE_WRITE: STD_LOGIC_VECTOR (7 downto 0) := 10100000;-器件地址写constant WRITE_DATA: STD_LOGIC_VECTOR (7 downto 0) := 11000011; -写入的数据constant BYTE_ADDR: STD_LOGIC_VECTOR (7 downto 0) := 00000011;-写入的地址type state is (IDLE,START1,ADD1,ACK1,ADD2,ACK2,STAR

5、T2,ADD3,ACK3,DATA,ACK4,STOP1,STOP2); signal cstate: state; signal temp_sw1,temp_sw2:Std_LOGIC; begin - process(clk,rst_n) 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 1 页，共 8 页 - - - - - - - - - begin if (rst_n = 0) then sw_state = 0; elsif (clkevent AND clk = 1) t

6、hen if(sw1_en = 1) then sw_state = 0; elsif (sw2_en = 1) then sw_state = 1; end if; end if; end process; - process(clk,rst_n) begin if (rst_n = 0) then cnt_delay = 0 & x00; elsif (clkevent AND clk = 1) then if(cnt_delay = 10#499#) then -相当于 500 分频，得到100K 时钟cnt_delay = 0 & x00; else cnt_delay = cnt_d

7、elay+1; end if; end if; end process; scl_pos = 1 when (cnt_delay = 10#499#) else 0; -IIC时钟上升沿scl_hig = 1 when (cnt_delay = 10#124#) else 0; -IIC时钟高电平scl_neg = 1 when (cnt_delay = 10#249#) else 0; -IIC时钟下降沿scl_low = 1 when (cnt_delay = 10#374#) else 0; -IIC时钟低电平process(clk,rst_n) begin if (rst_n = 0)

8、 then scl = 0; elsif (clkevent AND clk = 1) then if(scl_pos = 1) then scl = 1; elsif(scl_neg = 1) then scl = 0; end if; end if; end process; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 2 页，共 8 页 - - - - - - - - - - process(clk,rst_n) begin if (rst_n = 0) then csta

9、te = IDLE; sda_r = 1; sda_link = 0; num = x0; read_data sda_link = 1; sda_r = 1; if (sw1_en/=temp_sw1)or(sw2_en/=temp_sw2) then -当 sw1_en 和 sw2_en 变化一次，只读或写一次，避免多次读写temp_sw1=sw1_en;temp_sw2=sw2_en; if (sw1_en = 1) OR (sw2_en = 1) then db_r = DEVICE_WRITE; cstate = START1; else cstate = IDLE; end if;

10、 else cstate if (scl_hig = 1) then -起始位sda_link = 1;-数据线由sda_r 控制sda_r = 0; cstate = ADD1; num = x0; else cstate -器件地址 &0 if (scl_low = 1) then if (num = x8) then num = x0; sda_r = 1; sda_link = 0;-数据线设为高阻态，允许输入cstate = ACK1; else 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - -

11、 - - - - 第 3 页，共 8 页 - - - - - - - - - cstate = ADD1; num sda_r sda_r sda_r sda_r sda_r sda_r sda_r sda_r NULL; end case; end if; else cstate -应答if (scl_neg = 1) then cstate = ADD2; db_r = BYTE_ADDR; else cstate -要写入数据或读取数据的地址if (scl_low = 1) then if (num = x8) then num = x0; sda_r = 1; sda_link = 0

12、;-数据线设为高阻态，允许输入cstate = ACK2; else sda_link = 1;-数据线由sda_r 控制num = num+1; cstate sda_r sda_r sda_r sda_r sda_r sda_r sda_r sda_r NULL; end case; end if; else cstate -应答if (scl_neg = 1) then if (sw_state = 0) then -如果写入数据cstate = DATA; db_r = WRITE_DATA; elsif (sw_state = 1) then -如果读取数据db_r = DEVICE

13、_READ; cstate = START2; end if; else cstate -起始位if (scl_low = 1) then sda_link = 1; sda_r = 1; cstate = START2; elsif (scl_hig = 1) then sda_r = 0; cstate = ADD3; else cstate -器件地址 &1 if (scl_low =1) then if (num = x8) then num = x0; sda_r = 1; sda_link = 0; cstate = ACK3; l11=0; else num = num+1; c

14、state sda_r sda_r sda_r sda_r sda_r sda_r sda_r sda_r NULL; end case; end if; else cstate -应答if (scl_neg = 1) then cstate = DATA; sda_link = 0; else cstate if (sw_state = 1) then -如果是读数据if (num = x7) then cstate = DATA; if (scl_hig = 1) then num read_data(7) read_data(6) read_data(5) read_data(4) re

15、ad_data(3) read_data(2) read_data(1) read_data(0) NULL; end case; end if; elsif (scl_low = 1) AND (num = x8) then num = x0; cstate = ACK4; else 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 6 页，共 8 页 - - - - - - - - - cstate = DATA; end if; elsif (sw_state = 0) then

16、 -如果是写数据sda_link = 1; if (num = x7) then cstate = DATA; if (scl_low = 1) then sda_link = 1; num sda_r sda_r sda_r sda_r sda_r sda_r sda_r sda_r NULL; end case; end if; elsif (scl_Low = 1) AND (num = x8) then num = x0; sda_r = 1; sda_link = 0; cstate = ACK4; else cstate -应答if (scl_neg = 1) then cstat

17、e = STOP1; else cstate -停止位if(scl_low = 1) then sda_link = 1; sda_r = 0; cstate = STOP1; elsif (scl_hig = 1) then sda_r = 1; cstate = STOP2; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 7 页，共 8 页 - - - - - - - - - else cstate if (scl_low = 1) then sda_r = 1; else c

18、state cstate = IDLE; end case; end if; end process; process (sda, sda_link) begin if(sda_link = 1) then sda = sda_r; else sda = Z; end if; end process; sda_in = sda; -sda_in = z; -sda = sda_r when (sda_link = 1) else - z; dis_data = read_data; end architecture iic_communication; 名师资料总结 - - -精品资料欢迎下载 - - - - - - - - - - - - - - - - - - 名师精心整理 - - - - - - - 第 8 页，共 8 页 - - - - - - - - -