EDA数字电压表设计(7页).doc

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1、-数字电压表源程序：module shuzidianya(ale,start,oe,addr,seg,d,eoc,clk,clk1k);output ale,start,oe; /通道锁存，转换开始，输出允许output2:0 addr; /通道选择output7:0 seg; /数码管段选input7:0 d; /转换结果输入input eoc,clk,clk1k; /转换结束wire7:0 q;wire3:0 dec_in;adcint(ale,start,oe,addr,q,d,clk,eoc);segscan segscan(dec_in,q,clk1k);decoder decode

2、r(seg,dec_in);endmodule/ADC0809控制模块module adcint(ale,start,oe,addr,q,d,clk,eoc);output ale,start,oe;output2:0 addr;output7:0 q;input7:0 d;input clk,eoc;reg ale,start,oe;reg7:0 q;reg lock;reg4:0 present_state,next_state;parameter st0=5b00001, st1=5b00010, st2=5b00100, st3=5b01000, st4=5b10000;assign

3、addr=3b000;always (posedge clk)begin present_state=next_state;endalways (present_state or eoc)begin case(present_state)st0:next_state=st1;st1:next_state=st2;st2: begin if(eoc) next_state=st3; else next_state=st2; endst3:next_state=st4;st4:next_state=st0;default:next_state=st0;endcaseendalways (prese

4、nt_state) begin case(present_state) st0:begin ale=0;start=0;lock=0;oe=0;end st1:begin ale=1;start=1;lock=0;oe=0;end st2:begin ale=0;start=0;lock=0;oe=0;end st3:begin ale=0;start=0;lock=0;oe=1;end st4:begin ale=0;start=0;lock=1;oe=1;end default begin ale=0;start=0;lock=0;oe=0;end endcase endalways (p

5、osedge lock)begin q=d; endendmodulemodule weisaomiao(clk,sel1);input clk;output 1:0sel1;reg 1:0sel1;always (posedge clk )beginsel1=sel1+1; endendmodulemodule suocun( qo, din, load );output7:0 qo;input7:0 din;input load;reg7:0 qo;always ( posedge load )beginqo = din;endendmodulemodule segscan(dout,di

6、n,sel);output3:0 dout;input 7:0 din;input sel;reg3:0 dout;always (sel or din)begin if (sel) dout=din3:0; else dout=din7:4;endendmodule/显示译码模块module decoder(decoderout,dec_in);output7:0 decoderout;input3:0 dec_in;reg7:0 decoderout;always (dec_in)begin case(dec_in)4h0: decoderout=8b00111111;4h1: decod

7、erout=8b00000110;4h2: decoderout=8b01011011;4h3: decoderout=8b01001111;4h4: decoderout=8b01100110;4h5: decoderout=8b01101101;4h6: decoderout=8b01111101;4h7: decoderout=8b00000111;4h8: decoderout=8b01111111;4h9: decoderout=8b01101111;4ha: decoderout=8b01110111;4hb: decoderout=8b01111100;4hc: decoderout=8b00111001;4hd: decoderout=8b01011110;4he: decoderout=8b01111001;4hf: decoderout=8b01110001; endcase endendmodule第 7 页-