SPI四种模式区别(7页).doc

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1、-spi四种模式SPI的相位(CPHA)和极性(CPOL)分别可以为0或1，对应的4种组合构成了SPI的4种模式(mode)Mode 0 CPOL=0, CPHA=0Mode 1 CPOL=0, CPHA=1Mode 2 CPOL=1, CPHA=0Mode 3 CPOL=1, CPHA=1时钟极性CPOL: 即SPI空闲时，时钟信号SCLK的电平（1:空闲时高电平; 0:空闲时低电平）时钟相位CPHA: 即SPI在SCLK第几个边沿开始采样（0:第一个边沿开始; 1:第二个边沿开始）sd卡地spi常用的是mode 0 和mode 3，这两种模式的相同的地方是都在时钟上升沿采样传输数据，区别这

2、两种方式的简单方法就是看空闲时，时钟的电平状态，低电平为mode 0 ，高电平为mode 3。OverviewThe SPI standard includes four modes, defined by the polarity of SCLK and the phase relationship between data and SCLK. The clock polarity (CPOL) is determined by the idle state of SCLK. If the idle state is low, CPOL is 0. If the idle state is

3、high, CPOL is 1. The clock phase (CPHA) is determined by which edge that data is valid. If the data is valid on the first edge of SCLK, CPHA is 0. If the data is valid on the second edge of SCLK, CPHA is 1.Industry has two common formats to define the four SPI modes. The first format defines the fou

4、r possible combinations of phase and polarity as mode 0, mode 1, mode 2, and mode 3. The second format defines the combinations as mode 0,0, mode 0,1, mode 1,0, and mode 1,1. The SPI master must use a mode supported by the slave device to allow proper communications.Dallas Semiconductor/Maxims SPI-i

5、nterface RTCs support both SCLK polarities. The RTC automatically determines the polarity by detecting the idle state of SCLK when CE is asserted. The master must, therefore, place SCLK in the proper idle state before CE is asserted. Only one phase is supported. Since two SCLK polarities are support

6、ed, two of the four SPI modes are supported by the RTCs: modes 1 and 3 (mode 0,1 and mode 1,1).On microcontrollers with built-in SPI interfaces, an SPI control or configuration register will have bits that control the polarity and phase. Because the RTC supports either polarity, the polarity can be

7、set as desired. The phase bit, however, must be set properly, or the RTC will not operate correctly.Figure 1 shows a typical single-byte read and Figure 2 shows a typical single-byte write. Each time CE is asserted, the first eight SCLK pulses are used to clock in a command byte. The command byte co

8、nsists of several bits that define a register address, and one bit that defines the data direction: a write if the next eight SCLK pulses will clock data into the part, or a read if data is clocked out of the part. Additional groups of eight SCLK pulses continue to transfer data in the selected dire

9、ction until CE is deasserted.Note: In burst mode, CE is kept high and additional SCLK cycles are sent until the end of the burst.Figure 1. Single-byte read.Note: In burst mode, CE is kept high and additional SCLK cycles are sent until the end of the burst.Figure 2. Single-byte write.Examples of SPI code are available at: Real-Time Clocks SummaryThe information in this application note will help ensure that SPI communication routines will function correctly.第 7 页-