VHDL时钟程序(6页).doc

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1、-VHDL时钟程序-第 6 页library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Counter_m_f_s isport clk,reset : in std_logic ;bcd_h_m: out std_logic_vector(3 downto 0); -秒钟个位输出bcd_l_m: out std_logic_vector(3 downto 0); -秒钟十位输出bcd_l_f: out std_logic_vector(3 downto 0); -分钟个位输出bcd_h_f:

2、 out std_logic_vector(3 downto 0); -分钟十位输出bcd_l_s: out std_logic_vector(3 downto 0); -时钟个位输出bcd_h_s: out std_logic_vector(3 downto 0); -时钟十位输出up : out std_logicend Counter_m_f_s ;architecture behav of Counter_m_f_s issignal bcd_h_m_r : std_logic_vector(3 downto 0); -秒钟个位内部信号signal bcd_l_m_r : std_lo

3、gic_vector(3 downto 0); -秒钟十位内部信号signal bcd_h_f_r : std_logic_vector(3 downto 0); -分钟个位内部信号signal bcd_l_f_r : std_logic_vector(3 downto 0); -分钟十位内部信号signal bcd_h_s_r : std_logic_vector(3 downto 0); -时钟个位内部信号signal bcd_l_s_r : std_logic_vector(3 downto 0); -时钟个位内部信号signal up_r1 : std_logic;signal up_

4、r2 : std_logic;beginU1: process (clk, reset) -秒钟 begin if reset=0 then bcd_h_m_r =0000; bcd_l_m_r =0000; up_r1 =0;else if clkevent and clk=1 then if bcd_h_m_r =0101 and bcd_l_m_r =1001 then bcd_h_m_r =0000; -59秒，分钟进一 bcd_l_m_r =0000; up_r1 = 1 ; else if bcd_l_m_r(3 downto 0) = 1001 then -秒的个位为9，十位进一

5、，分钟不进为 bcd_l_m_r(3 downto 0)= 0000 ; bcd_h_m_r(3 downto 0) = bcd_h_m_r(3 downto 0) + 1 ; up_r1 = 0; else bcd_l_m_r(3 downto 0) = bcd_l_m_r(3 downto 0) + 1 ; up_r1 = 0; end if; end if; end if; end if; end process;bcd_h_m = bcd_h_m_r;bcd_l_m = bcd_l_m_r;U2: process (up_r1 , reset) -分钟 beginif reset=0

6、then bcd_h_f_r =0000; bcd_l_f_r =0000; up_r2 =0;else if up_r1event and up_r1=1 then if bcd_h_f_r =0101 and bcd_l_f_r =1001 then -59分，时钟进一 bcd_h_f_r =0000; bcd_l_f_r =0000; up_r2 = 1 ; else if bcd_l_f_r(3 downto 0) = 1001 then -分的个位为9，十位进一，时钟不进位 bcd_l_f_r(3 downto 0) = 0000 ; bcd_h_f_r(3 downto 0) =

7、bcd_h_f_r(3 downto 0) + 1 ; up_r2 = 0; else bcd_l_f_r(3 downto 0) = bcd_l_f_r(3 downto 0) + 1 ; up_r2 = 0; end if; end if; end if; end if; end process;bcd_h_f = bcd_h_f_r;bcd_l_f = bcd_l_f_r;U3: process ( up_r2 , reset) 时钟beginif reset=0 then bcd_h_s_r =0000; bcd_l_s_r =0000; up =0;else if up_r2even

8、t and up_r2=1 then if bcd_h_s_r =0010 and bcd_l_s_r =0011 then -23时，时钟进一。 bcd_h_s_r =0000; bcd_l_s_r =0000; up = 1 ; else if bcd_l_s_r(3 downto 0) = 1001 then bcd_l_s_r(3 downto 0)= 0000 ; bcd_h_s_r(3 downto 0) = bcd_h_s_r(3 downto 0) + 1 ; up = 0; else bcd_l_s_r(3 downto 0) = bcd_l_s_r(3 downto 0)

9、+ 1 ; up = 0; end if; end if; end if; end if; end process;bcd_h_s = bcd_h_s_r;bcd_l_s = bcd_l_s_r; end architecture behav;另外给大家数码管的驱动程序！LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_Unsigned.ALL;ENTITY showseg7 IS PORT(clk: IN STD_LOGIC;-d:in std_logic_vector(31 downto 0); seg0,seg1,se

10、g2,seg3,seg4,seg5,seg6,seg7,dig0,dig1,dig2,dig3,dig4,dig5,dig6,dig7:OUT STD_LOGICEND ENTITY showseg7;ARCHITECTURE one OF showseg7 IS SIGNAL count: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL seg_r: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL dig_r: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL data: STD_LOGIC_VECTOR(31 DO

11、WNTO 0); SIGNAL disp_r: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(clk) -1kHz BEGIN IF clkEVENT AND clk=1 THEN IF count=7 THEN count=count+1; ELSE count disp_r=data(31 DOWNTO 28);dig_r disp_r=data(27 DOWNTO 24);dig_r disp_r=data(23 DOWNTO 20);dig_r disp_r=data(19 DOWNTO 16);dig_r disp_r=data(15 DOWN

12、TO 12);dig_r disp_r=data(11 DOWNTO 8);dig_r disp_r=data(7 DOWNTO 4);dig_r disp_r=data(3 DOWNTO 0);dig_r NULL; END CASE; END PROCESS; PROCESS(disp_r) BEGIN CASE disp_r IS WHEN 0000 = seg_r seg_r seg_r seg_r seg_r seg_r seg_r seg_r seg_r seg_r seg_r seg_r seg_r seg_r seg_r seg_r NULL; END CASE; END PROCESS;seg0=seg_r(0); dig0=dig_r(0);seg1=seg_r(1); dig1=dig_r(1);seg2=seg_r(2); dig2=dig_r(2);seg3=seg_r(3); dig3=dig_r(3);seg4=seg_r(4); dig4=dig_r(4);seg5=seg_r(5); dig5=dig_r(5);seg6=seg_r(6); dig6=dig_r(6);seg7=seg_r(7); dig7=dig_r(7);end architecture one;