四位全加器的VHDL设计.ppt

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1、,四位全加器的VHDL设计,一位全加器真值表,一位全加器的逻辑表达式,S=ABCin Co=AB+BCin+ACin 其中A,B为要相加的数，Cin为进位输 入；S为和，Co是进位输出；,Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity fulladder Is Port(Ci,a,b : IN std_logic; s,Co : OUT std_logic); End fulladder; Architecture m1 Of fulladder Is Signal tmp:

2、std_logic_vector(1 downto 0); Begin tmp=(0 ,一位全加器的数据流（逻辑）描述,Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity fulladder is Port (A,B,CI:in std_logic; S,CO:out std_logic); End fulladder; Architecture dataflow of fulladder is Begin S= CI xor A xor B; CO= (A and B) or (

3、CI and A) or (CI and B); End dataflow;,一位全加器的行为描述,Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity fulladder is Port (a,b,cin: In bit; sum,cout: Out bit); End fulladder; Architecture behave Of fulladder Is Begin Process (a, b, cin) Begin If(a Or b Or cin)= 0 Then su

4、m =0; cout =0; Elsif (a AND b AND cin ) =1 Then sum =1; cout =1; Elsif (a XOR b XOR cin ) =0 Then sum =0; cout =1; Else sum =1; cout =0; End If; End Process; End behave;,4位全加器的设计，先设计4个1位的全加器，然后将低位的进位输出与高位的进位输入相连，将要进行加法运算的两个4位数的每一位分别作为每一个1位全加器的输入，进行加法运算，所有的1位全加器的输出组成一个4位数，即输入的两个4位数之和，最高位的全加器产生的进位输出即两

5、个4位数求和的进位输出。（如图）,Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity adder4 Is Port(Cin : IN std_logic; x, y : IN std_logic_vector(3 downto 0); sum : OUT std_logic_vector(3 downto 0); Cout : OUT std_logic); End adder4;,Architecture ax Of adder4 Is Signal c: std_logic_v

6、ector(0 to 4); Component fulladder Port(Ci,a,b : IN std_logic; s, Co : OUT std_logic); End component; Begin c(0)c(0),a=x(0),b=y(0), s=sum(0),Co=c(1); U2:fulladder Port Map(c(1),x(1),y(1),sum(1),c(2); U3:fulladder Port Map(c(2),x(2),y(2),sum(2),c(3); U4:fulladder Port Map(c(3),x(3),y(3),sum(3),c(4);

7、Cout=c(4); End ax;,library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder4bit is port(cin: in std_logic; a,b: in std_logic_vector(3 downto 0); s: out std_logic_vector(3 downto 0); cout: out std_logic ); end adder4bit; architecture beh of adder4bit is signal sint: std_logic_vector(4 downto 0); signal aa,bb: std_logic_vector(4 downto 0); begin aa=0 ,