数字电路课程设计报告数字钟设计.doc

《数字电路课程设计报告数字钟设计.doc》由会员分享，可在线阅读，更多相关《数字电路课程设计报告数字钟设计.doc（16页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、题目：数字钟设计1 设计要求1、设计一个数字钟，能够显示当前时间，分别用6个数码管显示小时、分钟、秒钟的时间，秒针的计数频率为1Hz，可由系统脉冲分频得到。2、在整点进行提示，可通过LED闪烁实现，闪烁频率及花型可自己设计。3、能够调整小时和分钟的时间，调整的形式为通过按键进行累加。4、具有闹钟功能，闹钟时间可以任意设定（设定的形式同样为通过按键累加），并且在设定的时间能够进行提示，提示同样可以由LED闪烁实现。2 设计分析及系统方案设计采用7个七段译码管，前6个显示时间，最后一个显示模式，通过模式04来实现正常计时，调时，调闹钟的功能作为控制模块。系统可分为分频模块，计时模块，译码管显示模块

2、，控制模块，报警控制模块，以及警报花型模块。结果框图如下：3系统以及模块硬件电路设计Node NameLocationNode NameLocationNode NameLocationclkPIN_N2hex41PIN_U1hex73PIN_Y22hex10PIN_L3hex42PIN_U2hex72PIN_W21hex11PIN_L2hex43PIN_T4hex71PIN_V21hex12PIN_L9hex44PIN_R7hex70PIN_V20hex13PIN_L6hex45PIN_R6hex80PIN_AF10hex14PIN_L7hex46PIN_T3hex81PIN_AB12hex

3、15PIN_P9hex50PIN_Y23hex82PIN_AC12hex16PIN_N9hex51PIN_AA25hex83PIN_AD11hex20PIN_R2hex52PIN_AA26hex84PIN_AE11hex21PIN_P4hex53PIN_Y26hex85PIN_V14hex22PIN_P3hex54PIN_Y25hex86PIN_V13hex23PIN_M2hex55PIN_U22key2PIN_P23hex24PIN_M3hex56PIN_W24key3PIN_W26hex25PIN_M5hex60PIN_AB23pausePIN_V2hex26PIN_M4hex61PIN_

4、V22resetPIN_V1hex30PIN_T2hex62PIN_AC25tip3PIN_U18hex31PIN_P6hex63PIN_AC26tip2PIN_U17hex32PIN_P7hex64PIN_AB26tip1PIN_AA20hex33PIN_T9hex65PIN_AB25tip0PIN_Y18hex34PIN_R5hex66PIN_Y24key1PIN_N23hex35PIN_R4hex76PIN_AB24hex36PIN_R3hex75PIN_AA23hex40PIN_U9hex74PIN_AA244 系统的Verilog HDL设计module clock (hex8,he

5、x7,hex6,hex5,hex4,hex3,hex2,hex1,reset,clk,pause,tip,key3,key2);output 6:0 hex8;output 6:0 hex7;output 6:0 hex6;output 6:0 hex5;output 6:0 hex4;output 6:0 hex3;output 6:0 hex2;output 6:0 hex1;output 3:0 tip;input key3,key2; /key3调节模式，key2用来控制调节的量input reset;input clk;input pause; /当pause=1时停止计数（数字钟暂

6、停）wire m_p,h_p; /进位或调时时产生上升沿，分别控制分钟和时钟的增加reg 3:0tip; /报警时的ledreg 6:0hex8;reg 6:0hex7;reg 6:0hex6;reg 6:0hex5;reg 6:0hex4;reg 6:0hex3;reg 6:0hex2;reg 6:0hex1;reg 2:0qout8; /表示模式reg 3:0qout7;reg 3:0qout6; /qout1至qout6为时钟显示时间reg 3:0qout5;reg 3:0qout4;reg 3:0qout3;reg 3:0qout2;reg 3:0qout1;reg rco4;reg

7、rco2;reg rcoc;reg clka;reg ctr;reg alert1,alert2;reg2:0 mode;reg24:0 temp;reg23:0 temp1;reg9:0 temp2;reg7:0 second;reg7:0 min; /闹钟时间reg7:0 minute; /实际时间reg7:0 h; /闹钟时间reg7:0 hour; /实际时间assignm_p=rco4 | !key2;assign h_p=rco2 | !key2;always (posedge clk) /分频得到1Hz频率begin if(temp=24999999) begintemp=0;c

8、lka=!clka;end elsetemp=temp+1;hex7=7b1111111;endalways (posedge clk) /得到4Hz频率begin if(temp1=3124999) begintemp1=0;ctr=!ctr;end elsetemp1=temp1+1;endalways (posedge key3) /mode=3b010时调节时钟,3b001时调节分钟,3b011时调节闹钟时钟，3b100时设置闹钟时钟，通过hex8显示beginif(mode=3b100)mode=3b000;elsemode=mode+1b1;qout8=mode;endalways

9、 (posedge clka or posedge reset) /秒beginif(reset=1)second=4b0000;else if(pause=1)second=second;else if(second=59)beginsecond=4b0000;rco4=1b1;endelsebeginsecond=second+1;rco4=1b0;endqout5=second/10;qout6=second%10;end/* 7段译码管时间显示模块 */always (qout8) /显示modebegincase(qout8)3b100:hex8=7b1000000;3b000:he

10、x8=7b1111001;3b001:hex8=7b0100100;3b010:hex8=7b0110000;3b011:hex8=7b0011001;default: hex8=7b1111111;endcaseendalways (qout6)begincase(qout6)4b0000:hex6=7b1000000;4b0001:hex6=7b1111001;4b0010:hex6=7b0100100;4b0011:hex6=7b0110000;4b0100:hex6=7b0011001;4b0101:hex6=7b0010010;4b0110:hex6=7b0000011;4b0111

11、:hex6=7b1111000;4b1000:hex6=7b0000000;4b1001:hex6=7b0011000;default: hex6=7b1000000;endcaseendalways (qout5)begincase(qout5)4b0000:hex5=7b1000000;4b0001:hex5=7b1111001;4b0010:hex5=7b0100100;4b0011:hex5=7b0110000;4b0100:hex5=7b0011001;4b0101:hex5=7b0010010;4b0110:hex5=7b0000011;default: hex5=7b100000

12、0;endcaseendalways (qout4)begincase(qout4)4b0000:hex4=7b1000000;4b0001:hex4=7b1111001;4b0010:hex4=7b0100100;4b0011:hex4=7b0110000;4b0100:hex4=7b0011001;4b0101:hex4=7b0010010;4b0110:hex4=7b0000011;4b0111:hex4=7b1111000;4b1000:hex4=7b0000000;4b1001:hex4=7b0011000;default: hex4=7b1000000;endcaseendalwa

13、ys (qout3)begincase(qout3)4b0000:hex3=7b1000000;4b0001:hex3=7b1111001;4b0010:hex3=7b0100100;4b0011:hex3=7b0110000;4b0100:hex3=7b0011001;4b0101:hex3=7b0010010;4b0110:hex3=7b0000011;default: hex3=7b1000000;endcaseendalways (qout2)begincase(qout2)4b0000:hex2=7b1000000;4b0001:hex2=7b1111001;4b0010:hex2=

14、7b0100100;4b0011:hex2=7b0110000;4b0100:hex2=7b0011001;4b0101:hex2=7b0010010;4b0110:hex2=7b0000011;4b0111:hex2=7b1111000;4b1000:hex2=7b0000000;4b1001:hex2=7b0011000;default: hex2=7b1000000;endcaseendalways (qout1)begincase(qout1)4b0000:hex1=7b1000000;4b0001:hex1=7b1111001;4b0010:hex1=7b0100100;4b0011

15、:hex1=7b0110000;4b0100:hex1=7b0011001;4b0101:hex1=7b0010010;4b0110:hex1=7b0000011;default: hex1=7b1000000;endcaseend/* * */always (posedge m_p or posedge reset ) /分beginif(reset=1)beginminute=0;qout3=minute/10;qout4=minute%10;endelsebegincase(mode)3b000:beginminute=(minute=59)? 0:(minute+1);rco2=(!m

16、inute & !second )? 1:0;qout3=minute/10;qout4=minute%10;end3b001:beginminute=(minute=59)? 0:(minute+1);rco2=(!minute & !second )? 1:0;qout3=minute/10;qout4=minute%10;end3b100: minute=minute;3b010:minute=minute;default:beginmin=(min=59)? 0:(min+1);qout3=min/10;qout4=min%10;endendcaseendendalways (pose

17、dge h_p or posedge reset) /时beginif(reset=1)beginhour=0;qout1=hour/10;qout2=hour%10;endelsebegincase(mode)3b010:beginhour=23)? 0:(hour+1);qout1=hour/10;qout2=hour%10;end3b000:beginhour=23)? 0:(hour+1);qout1=hour/10;qout2=hour%10;end3b011: beginhour=hour;end3b001:beginhour=hour;enddefault:beginh=23)?

18、 0:(h+1);qout1=h/10;qout2=h%10;endendcaseendendalways(qout1 or qout2 or qout3 or qout4 or temp2) /闹钟报时beginif(min=minute)beginif(h=hour)alert2=0;elsealert2=0;endelsealert2=0;endalways (posedge ctr) beginif(alert1=1)beginif(pause=1)temp2=temp2;else if(temp2=239)temp2=0;elsetemp2=temp2+1;endelse if(al

19、ert2=1)beginif(pause=1)temp2=temp2;else if(temp2=239)temp2=0;elsetemp2=temp2+1;endelsetemp2=0;endalways (!minute) /报告整点beginif(!minute=1)alert1=1;else alert1=0;endalways (posedge alert1 or posedge ctr or posedge alert2) /报告花型begin if(alert1=1)beginif(temp2=1)begintip=4b0101;endelse if(temp2=0)begint

20、ip3=0;tip2=0;tip1=0;tip0=0;endelsebegintip3=!tip3;tip2=!tip2;tip1=!tip1;tip0=!tip0;endendelse if(alert2=1)beginif(temp2=1)begintip=4b0101;endelse if(temp2=0)begintip3=0;tip2=0;tip1=0;tip0=0;endelsebegintip3=!tip3;tip2=!tip2;tip1=!tip1;tip0=!tip0;endendelsetip=4b0; endendmodule5 结论以及结果说明软件：Quartus II

21、计算机平台：Windows XP硬件：DE2 Development and Education Board结果说明：经测试当通过key3按键调整mode=0时，可以实现正常的计数即时钟功能，mode=1时可以实现调节分钟，mode=2时可以实现调节时钟，mode=3时可以实现设置闹钟分钟，mode=4时可以实现设置闹钟时钟，设置闹钟时相应闹钟时间在译码管上显示不影响时钟时间，当时钟分钟改变时相应显示分钟的译码管恢复显示为实际分钟时间。不足之处在于为了保证设置完闹钟后尽快七段译码管显示正常时钟，需要先设置闹钟时钟后设置闹钟分钟，否则要过一个小时才显示回正常的时钟。整点报时和闹钟报时的花型与所设定有不同，未能最终解决。编程过程通过不断的错误与搜索相关verilog注意事项，解决了诸如多驱动，不能匹配所有操作数的问题，认识到了verilog作为硬件编程语言的独特之处即需要考虑数字电路实现的问题。参考文献1王兢，戚金清.数字电路与系统.北京:电子工业出版社，20162夏宇闻. Verilog 数字系统设计教程（第三版）.北京：北京航空航天大学出版社，201316 / 16