2022年电子信息类英文资料加翻译 .pdf

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1、Sequential Logic Test 1.1 INTRODUCTION The previous chapter examined methods for creating sensitized paths in combina-tional logic extending from stuck-at faults on logic gates to observable outputs.We now attempt to create tests for sequential circuits where the outputs are a function not just of p

2、resent inputs but of past inputs as well.The objective will be the same:to create a sensitized path from the point where a fault occurs to an observable out-put.However,there are new factors that must be taken into consideration.A sensi-tized path must now be propagated not only through logic operat

3、ors,but also through an entirely new dimension time.The time dimension may be discrete,as in synchronous logic,or it may be continuous,as in asynchronous logic.The time dimension was ignored when creating tests for faults in combinational logic.It was implicitlyassu med that the output response woul

4、d stabilize before being measured with test equipment,and it was generally assumed that each test pat-tern was independent of its predecessors.As will be seen,the effects of time cannot be ignored,because t his added dimension greatly in?uences the results of test pat-tern generation and can complic

5、ate,by orders of magnitude,the problem of creating tests.Assumptions about circuit behavior must be carefully analyzed to determine the circumstances under which they prevail.1.2 TEST PROBLEMS CAUSED BY SEQUENTIAL LOGIC Two factors complicate the task of creating tests for sequential logic:memory an

6、d circuit delay.In sequential circuits the signals must not only be logically correct,but must also occur in the correct time sequence relative to other signals.The test prob-lem is further complicated by the fact that aberrant behavior can occur in sequential circuits when individual discrete compo

7、nents are all fault-free and conform to their manufacturers speci?cations.We?rst consider problems caused by the presence of memory,and then we examine the effects of circuit delay on the test generation problem.1.2.1 The Effects of Memory In the?rst chapter it was pointed out that,for combinational

8、 circuits,it was possible(but not necessarily reasonable)to create a complete test for logic faults by applying all possible binary combinations to the inputs of a circuit.That,as we shall see,is not true for circuits with memory.They may not only require more than 2 tests,but are also sensitive to

9、the order in which stimuli are applied.Test Vector Ordering The effects of memory can be seen from analysis of the cross-coupled NAND latch cf.Figure 2.3(b).Four faults will be considered,these 名师资料总结-精品资料欢迎下载-名师精心整理-第 1 页，共 16 页 -being the input SA1 faults on each of the two NAND gates(numbering is

10、 from top to bottom in the diagram).All four possible binary combinations are applied to the inputs in ascending order that is,in the sequence(Set,Reset)=(0,0),(0,1),(1,0),(1,1).We get the following response for the fault-free circuit(FF)and the circuit corresponding to each of the four input SA1 fa

11、ults.Input Output Set Reset FF 1 2 3 4 0 0 1 0 1 1 1 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 In this table,fault number 2 responds to the sequence of input vectors with an output response that exactly matches the fault-free circuit response.Clearly,this sequence of inputs will not distinguish betw

12、een the fault-free circuit and a circuit with input 2 SA1.The sequence is now applied in the exact opposite order.We get:Input Output Set Reset FF 1 2 3 4 1 1?0 1?1 0 0 0 0 0?0 1 1 0 1 1 1 0 0 1 0 1 1 1 The Indeterminate Value When the four input combinations are applied in reverse order,question ma

13、rks appear in some table positions.What is their signi?-cance?To answer this question,we take note of a situation that did not exist when dealing only with combinational logic;the cross-coupled NAND latch has memory.By virtue of feedback present in the circuit,it is able to remember the value of a s

14、ig-nal that was applied to the set input even after that signal is removed.Because of the feedback,neither the Set nor the Reset line need be held low any longer than necessary to effectively latch the circuit.However,when power is?rst applied to the circuit,it is not known what value is contained i

15、n the latch.How can circuit behavior be simulated when it is not known what value is contained in its memory?In real circuits,memory elements such as latches and?ip-?ops have indetermi-nate values when power is?rst applied.The contents of these elements remain indeterminate until the latch or?ip-?op

16、 is either set or reset to a known value.In a simulation model this condition is imitated by initializing circuit elements to the indeterminate X state.Then,as seen in Chapter 2,some signal values can drive a 名师资料总结-精品资料欢迎下载-名师精心整理-第 2 页，共 16 页 -logic element to a known state despite the presence of

17、 indeterminate values on other inputs.For example,the AND gate in Figure 2.1(c)responds with a 0 when any single input receives a 0,regardless of what values are present on other inputs.However,if a 1 is applied while all other inputs are at X,the output remains at X.Returning to the latch,the?rst s

18、equence began by applying 0s to both inputs,while the second sequence began by applying 1s to both inputs.In both cases the internal nets were initially indeterminate.The 0s in the?rst sequence were able to drive the latch to a known state,making it possible to immediately distinguish between correc

19、t and incorrect response.When applying the patterns in reverse order,it took longer to drive the latch into a state where good circuit response could be dis-tinguished from faulty circuit response.As a result,only one of the four faults is detected,namely,fault 1.Circuits with faults 2 and 3 agree w

20、ith the good circuit response in all instances where the good circuit has a known response.On the?rst pattern the good circuit respons is indeterminate and the circuit with fault 2 responds with a 0.The circuit with fault 3 responds with a 1.Since it is not known what value to expect from the good c

21、ircuit,there is no way to decide whether the faulted circuits are responding correctly.Faulted circuit 4 presents an additional complication.Its response is indetermi-nate for both the?rst and second patterns.However,because the good circuit has a known response to pattern 2,we do know what to look

22、for in the good circuit,namely,the value 0.Therefore,if a NAND latch is being tested with the second set of stimuli,and it is faulted with input 4 SA1,it might come up initially with a 0 on its output when power is applied to the circuit,in which case the faul is not detected,or it could come up wit

23、h a 1,in which case the fault will be detected.Oscillations Another complication resulting from the presence of memory is oscillations.Suppose that we?rst apply the test vector(0,0)to the cross-coupled NAND latch.Both NAND gates respond with a logic 1 on their outputs.We then apply the combination(1

24、,1)to the inputs.Now there are 1s on both inputs to each of the two NAND gatesbut not for long.The NAND gates transform these 1s into 0s on the outputs.The 0s then show up on the NAND inputs and cause the NAND out-puts to go to 1s.The cycle is repetitive;the latch is oscillating.We do not know what

25、value to expect on the NAND gate outputs;the latch may continue to oscillate until a different stimulus is applied to the inputs or the oscillations may eventually subside If the oscillations do subside,there is no practical way to predict,from a logic description of the circuit,the?nal state into w

26、hich the latch settles.Therefore,the NAND outputs are set to the indeterminate X.Probable Detected Faults When we analyzed the effectivenes of binary sequences applied to the NAND latch in descending order,we could not claim with certainty that stuck-at fault number 4 would be detected.Fortunately,t

27、hat fault is detected when the vectors are applied in ascending order.In other circuits the ambi-guity remains.In Figure 2.4(b)the Data input is complemented and both true and 名师资料总结-精品资料欢迎下载-名师精心整理-第 3 页，共 16 页 -complement values are applied to the latch.Barring the presence of a fault,the latch wi

28、ll not oscillate.However,when attempting to create a test for the circuit,we encounter another problem.If the Enable signal is SA1,the output of the inverter driven by Enable is permanently at 0 and the NAND gates driven by the inverter are permanently in a 1 state;hence the faulted latch cannot be

29、initialized to a known state.Indeterminate states were set on the latch nodes prior to the start of test pattern generation and the states remain indeterminate for the faulted circuit.If power is applied to the fault-free and faulted latches,the circuits may just happen to come up in the same state.

30、The problem just described is inherent in any?nite-state machine(FSM).The FSM is characterized by a set of states Q=q,q,.,q,a set of input stimuli 1 2 s I=i,i,.,i,another set Y=y,y,.,y of output responses,and a pair of 1 2 n 1 2 m Mappings M:Q I Q Z:Q I YThese mappings de?ne the next state transitio

31、n and the output behavior in response to any particular input stimulus.These mappings assume knowledge of the current state of the FSM at the time the stimulus is applied.When the initial stimulus is applied,that state is unknown unless some independent means such as a reset exists for driving the F

32、SM into a known state.In general,if there is no independent means for initializing an FSM,and if the Clock or Enable input is faulty,then it is not possible to apply just a single stimu-lus to the FSM and detect the presence of that fault.One approach used in industry is to mark a fault as a probabl

33、e detect if the fault-free circuit drives an output pin to a known logic state and the fault causes that same pin to assume an unknown state.The industry is not in complete agreement concerning the classi?cation of proba-ble detected faults.While some test engineers maintain that such a fault is lik

34、ely to eventually become detected,others argue that it should remain classi?ed as undetec-ted,and still others prefer to view it as a probable detect.If the probable detected fault is marked as detected,then there is a concern that an ATPG may be designed to ignore the fault and not try to create a

35、test for it in those situations where a test exists.The Initialization Problem Consider the circuit of Figure 5.1.During simula-tion,circuit operation begins with the D?ip-?op in an unknown state.In normal operation,when the input combination A=B=C=0 is applied and the?ip-?op is clocked,the Q output

36、 switches to 0.The?ip-?op can then be clocked a second time to obtain a test for the lower input of gate 3 SA1.If it is SA1,the expected value is Q=1;and if it is fault-free,the expected value is Q=0.Unfortunately,the test has a serious?aw!If the lower input to gate 3 is SA1,the 名师资料总结-精品资料欢迎下载-名师精心

37、整理-第 4 页，共 16 页 -output of the?ip-?op at the end of the?rst clock period is indeterminate because the value at the middle input to gate 3 is initially indeterminate.It is driven by the?ip-?op that has an indeterminate value.After a second clock pulse the value at Q will remain at X;hence it may agre

38、e with the good circuit response despite the presence of the fault.The fallacy lies in assuming correct circuit behavior when setting up the?ip-?op for the test.We depended upon correct behavior of the very net that we are attempting to test when setting up a test to detect a fault on that net.To co

39、rrectly establish a test,it is necessary to assume an indeterminate value from the?ip-?op.Then,from the D-algorithm,we know that the?ip-?op must be driven into the 0 state,without depending on the input to gate 3 that is driven by the?ip-?op.The?ip-?op value can then be used in conjunction with the

40、inputs to test for the SA1 on the lower input of gate 3.In this instance,we can set A=C=0,B=1.Then a 1 can be clocke d into the?ip-?op from gate 2.This produces a 0 on the out-put of the?ip-?op which can then be used with the assignment A=B=0 to clock a 0 into the?ip-?op.Now,with Q=0 and A=B=C=0,ano

41、ther clock causes D to appear on the output of the?ip-?op.Notice that input C was used,but it was used to set up gate 2.If input C were faulted in such a way as to affect both gates 2 and 3,then it could not have been used to set up the test.1.2.2 Timing Considerations Until now we have assumed that

42、 erroneous behavior on circuit outputs was the result of logic faults.Those faults generall result from actual physical defects such as opens or shorts,or incorrect fabrication such as an incorrect connection or a wrong component.Unfortunately,this assumption,while convenient,is an oversimpli?ca-tio

43、n.An error may indeed be a result of one or more logic faults,but it may also be the case that an error occurs and none of the above situations exists.Defects exist that can prevent an element from behaving in accordance with its speci?cations.Faults that affect the performance of a circuit are refe

44、rred to as para-metric faults,in contrast to the logic faults that have been considered up to this point.Parametric faults can affect voltage and current levels,and they can affect gain and switching speed of a circuit.Parametric faults in components can result from improper fabrication or from degr

45、adation as a consequence of a normal aging process.Environmental conditions such as temperature extremes,humidity,or mechanical vibration can accelerate the degradation process.Design oversights canproduce symptoms similar to parametric faults.Design problems include failure to take into account wir

46、e lengths,loading of devices,inad-equate decoupling,and failure to consider worst-case conditions such as maximum or minimum voltages or temperatures over which a device may be required to oper-ate.It is possible that none of these factors may cause an error in a particular design in a well-controll

47、ed environment,and yet any of these factors can destabilize a cir-cuit that is operating under adverse conditions.Relative timing between signal paths or the ability of the circuit to drive other circuits could be affected.Intermit tenterrors are particularly insidious because of their rather elusiv

48、e 名师资料总结-精品资料欢迎下载-名师精心整理-第 5 页，共 16 页 -nature,appearing only under particular combinations of circumstances.For exam-ple,a logic board may be designed for nominal signal delay for each component as a safety margin.Statistically,the delays should seldom accumulate so as to exceed a critical threshold

49、.However,as with any statistical expectation,there will occasion-ally be a circuit that does exceed the maximum permissible value.Worse still,it may work well at nominal voltages and/or temperatures and fail only when voltages and/or temperatures stray from their nominal value.A new board substitute

50、d for the orig-inal board may be closer to tolerance and work well under the degraded voltage and or temperature conditions.The original board may then,when checked at a depot or a board tester under ideal operating conditions,test satisfactorily.Consider the effects of timing variations on the dela