液晶显示器驱动IC原理和介绍.pdf

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1、液晶顯示器驅動液晶顯示器驅動ICIC原理和介紹原理和介紹 主講人主講人 :黃雲朋黃雲朋 ContentContent I.液晶 驅動 原 理 介紹 II.STN LCD Driver Introduction III.STN Case Study VI.TFT LCD Driver Introduction V.TFT Driver IC Consideration 液晶 驅動 原 理 Field OFF Field ON I.I.液晶液晶 驅動驅動 原原 理理 介紹介紹 Field OFF Field ON Twist Nematic(TN)STN TN DV1 DV2 PS:TN more

2、 suitable for more gray levels STN for black&white TN&STN V-T Transfer Curve V T Vsig Vc Vs Vc Vs Vc-Vs Vsig ON OFF ON LC Cell LCD 靜態驅動靜態驅動 法法 Mobile Phone Market Forecast Market Forecast 0 010010020020030030040040050050060060020002000200120012002200220032003STN MonoSTN MonoSTN ColorSTN ColorLTPS Co

3、lorLTPS ColorMobile Phone Msets II.STN LCD Driver introduction Driver introduction PDA Ksets 0 0200020004000400060006000800080001000010000120001200020002000200120012002200220032003STN MonoSTN MonoSTN ColorSTN ColorSTN PDA Market Forecast Market Forecast STN LCD Driver Introduction Driver Introductio

4、n Common Driver Segment Driver Shift Register Data Latch EI/O EO/I D0D8 Data Latch LP Output Stage V1V4 To STN segme Dclk Shift Register EI/O EO/I Output Stage VEE Vss To STN Common Dclk STN Common Driver STN Segment Driver STN LCD Driver Block Driver Block Line1 Line2 Line3 Common Signal Segment Si

5、gnal Column 1 Column 2 Column 1 Column 2 F+D F+D F-D -D +D -D +D -D +D STN LCD Driving waveformDriving waveform ON=(F+D)+(N-1)D N 2 2 OFF=(F-D)+(N-1)D N 2 2 SR=ON OFF F D =N SR=N +1 N -1 1.1 1.0 1.2 1.3 100 200 N Bias SR 2 1:2 2.23 4 1:3 1.73 8 1:4 1.45 16 1:5 1.29 32 1:7 1.2 64 1:9 1.15 100 1:11 1.

6、11 128 1:12 1.09 200 1:15 1.08 240 1:16 1.06 400 1:17 1.06 Limitation on STN LCD ResolutionResolution F 0 D-D-F F+D-D D-(F+D)F+D D F 0 2D 0 F+D F-D F+D-(F+D)D-D Common Segement LCD pixel STN LCD Driving Method APT IAPT Color on STN LCD -FRC Frame rate control =Time 4/4 3/4 2/4 1/4 0/4 Color on STN L

7、CD-PWM Common Segment Pixel Pulse Width Modulation Vertical Cross talk of STN LCDs M Common A B A pixel B pixel A B Reduce Vertical Crosstalk of STN LCDs M Common A B A pixel B pixel M Common A B A pixel B pixel Horizontal Cross talk of STN LCDs A B SEG L Line Common Pixel Waveform A B L SEG Drivers

8、 COM Drivers Com Output Status select circuit Display data latch circuit Display data RAM 132x65 Line address circuit I/O buffer Page address circuit Column address circuit Display Timing generation circuit CMOS OSC Status Bus holder Command decoder Power Supply Circuit MPU interface Vss VDD V1 V2 V

9、3 V4 CAP1+CAP1-CAP2+CAP2-CAP3+COUT SEG0SEG131 COM0COM63 Epson SED1565 Block Diagram Epson Voltage Reference Block Vdd V5 Vout (from charge pump)V1 V4 V3 V2 Vdd To Segment&Common Epson OSC Block V=VTn+VTp Power for OSC 1024x768 260K LCD panel WFP2373 Gate Driver Source Driver Source Driver 258 WFP237

10、3 Gate Driver 258 LCD Control ASIC Reference generator Or from Notebook LVDS LCD Controller(Panel Link Or ADC)from Desktop PC VI.TFT LCD Block Diagram Block Diagram TFT LCD Market Forecast Market Forecast Msets 0 05 51010151520202525303035354040454520002000200120012002200220032003LD MonitorLD Monito

11、rNotebookNotebookLCD TVLCD TVNumber of Drivers Required Number of Drivers Required Gate Driver Output Format VGA SVGA XGA SXGA UGA 120/128 4 5 6 8 10 150/154 4 5 8 192/200 3 4 6 256/258 3 4 No.of Drivers Required Source Driver Output Format VGA SVGA XGA SXGA UGA 240 8 10 16 20 300/309 10 384 5 8 10

12、402 6 12 No.of Drivers Required VGA 640X480 SVGA 800X600 XGA 1024X768 SXGA 1280X1024 UGA 1600X1200 TFT LCD Panel Structure Panel Structure PCB LSI Glass Substrate(TFT LCD)TCP Copper-foil lead line Soldering Anisotropic Conducting film Gold bump Gate electrode conducting line Source electrode conduct

13、ing line Sealant TFT Liquid crystal Source Driver Gate Driver Clcd Cstore TFT LCDs Pixel Schematic TFT LCD Driver Introduction Driver Introduction Source Bus Gate Bus Cstore 1 2 3 4 5 1 +2 +3 +4 +5 +Frame N Columns Rows 1 2 3 4 5 1 -2 -3 -4 -5 -Frame N+1 Columns Rows 1 2 3 4 5 1 +2 -3 +4 -5 +Frame N

14、 Columns Rows 1 2 3 4 5 1 +2 -3 +4 -5 +Frame N+1 Columns Rows 1 2 3 4 5 1 +-+-+2 +-+-+3 +-+-+4 +-+-+5 +-+-+Frame N Columns Rows 1 2 3 4 5 1 -+-+-2 -+-+-3 -+-+-4 -+-+-5 -+-+-Frame N+1 Columns Rows 1 2 3 4 5 1 +-+-+2 -+-+-3 +-+-+4 -+-+-5 +-+-+Frame N Columns Rows 1 2 3 4 5 1 -+-+-2 +-+-+3 -+-+-4 +-+-+

15、5 -+-+-Frame N+1 Columns Rows Frame Inversion Row Inversion Column Inversion Dot Inversion TFT LCD Driving Method 200 400 600 800 1000 Row Column Pixel (Old)Pixel (New)Inversion Method Pd mW/System SVGA Power due to Column Driving Function 258 bits bidirection shift register Decoder Output Buffer DI

16、/O1 DO/I1 CLK U/D XDOFF VEE1 VEE2 OUT0 OUT257 OUT2 258 bits bidirection shift register DI/O2 DO/I2 XDON OEN VDD Gate Driver Block Diagram VDD VCC VSS VEE2 VEE1 CLK DI/O2 XDON XDOFF OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 DI/O1 OUT256 OUT257 1 2 3 4 5 3 Level Gate Driver Timing Diagram Gate bus Cgd V Gate

17、-Cell Cross-Coupling V=Cgd Cs Clc Cgd+Clc+Cs *Vgate Cgd Cs on Gate Cell&Three Level Gate Driver Cgd Gate(n-1)Gate(n)Data Data V1 V2 Cs Clc V=Cgd*Cgd+Clc+Cs V1-Cs*V2 Cgd*V1=Cs*V2 64 bits bidirection shift register 384 bytes data register Synchronous latch D/A converter Output Buffer DI/O DO/I CLK U/D

18、 INV D00 to 07 D10 to 17 D20 to 27 D30 to 37 D40 to 47 D50 to 57 LOAD POL V0 to V9 VDD1 VSS 1 VDD2 VSS 2 OUT1 OUT384 OUT2 Source Driver Block Diagram CLK DI/O DO/I D00D57 LOAD POL OUT1 OUT384 Preset to middle level First data Last data Next first data Source Driver Timing Diagram Diagram Vcom V6 V5

19、V4 V3 V2 V1 V0 V0 V1 V2 V3 V4 V5 V6 Gary level one line Direct Driving of TFT LCDs Gate Signal Vcom V6 V5 V4 V3 V2 V1 V0 V0 V1 V2 V3 V4 V5 V6 V7 V7 AC Modulation Driving of TFT LCDs Gate Pulse transmission Delay N TFT Panel Gate Line RC model Horizontal Cross talk of TFT LCDs(1)A B A B Vcom Effectiv

20、e Vcom Horizontal Cross talk of TFT LCDs(2)A B A B Vcom Effective Vcom Vertical Cross talk of STN LCDs Pixel Gate Line Source Line Frame/Line Inversion Charging Path Cgd Cs Clc Gate Driver N-1 Gate Driver N Source Driver N-1 Cgd Cs Clc Source Driver N Cgd Cs Clc Source Driver N+1 Common Plate Column

21、/Dot Inversion Charging Path Cgd Cs Clc Gate Driver N-1 Gate Driver N Source Driver N-1 Cgd Cs Clc Source Driver N Cgd Cs Clc Source Driver N+1 Common Plate Comparison of Addressing Method Frame Inversion Row Inversion Column Inversion Dot Inversion Vcom AC Modulation AC Modulation DC DC Output Volt

22、age Low Low High High Power consumption Low High Low High Image Quality Poor Horizontal Cross talk Vertical Cross talk Good Shift Register Video In LP EI/O EO/I Q1 Q2 Q3 Q4 Q5 Analog Source Driver I TFT LCD Driver structure Shift Register Video In LP EI/O EO/I Q1 Q2 Q3 Q4 Q5 Analog Source Driver II

23、Sample&Hold ck1 ck2 ck3 ck4 LP CK1 CK2 Q3 CK3 CK4 Analog Source Driver Buffer Stage External reference V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 R0 to R63 R255 to R192 R191 to R128 R127 to R64 R63 to R0 R64 to R127 R128 to R191 R191 to R255 Digital Source Driver I DAC1 DAC2 DAC383 DAC384 decoder External refere

24、nce V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 R0 to R63 R255 to R192 R191 to R128 R127 to R64 R63 to R0 R64 to R127 R128 to R191 R191 to R255 Digital Source Driver II DAC1 DAC2 DAC383 DAC384 decoder V.TFT LCD Driver Consideration 1.Output Accuracy(6bits,8bits)2.Power consumption(portable)3.Die size(Cost)Perform

25、ance requirement 1.High accuracy Resistor String 2.Digital method to reduce power 3.Power Arrangement 4.Reduce decoder size 5.Output Structure to reduce chip size 6.Approach higher output voltage 7.Charge conservation to save power TFT LCD Driver Design Consideration V0 V9 1000 Resistor unit 64 gray

26、 level to DAC 1.High Accuracy Resistor String V T LCD Panel Eio1 Eio2 Eio1 Eio2 Eio1 Eio2 Eio1 Eio2 Eio R(0:5)G(0:5)B(0:5)Clk 2.Power Consumption Improve Method I Eio1 Eio2 R(0:5)G(0:5)B(0:5)Clk Control Logic DFF DFF DFF DFF DFF End token CL1 CL2 Eio1 Eio2 Control Logic DFF DFF DFF DFF DFF End token

27、 CL1 CL2 Power Consumption Improve Method I Source driver 1 Source driver 2 Cont.Eio1 Eio2 DFF DFF DFF DFF DFF DFF DFF control control control Block 1 Block 2 Block 3 Block N EIO CLK R(0:5)G(0:5)B(0:5)2.Power Consumption Improve Method II Cont.CLK&control Data Input Buffer Shift Register Data Regist

28、ers 64 Decoder Cells 64 Level Shifters 64 Switches 64 Decoder Cells 64 Level Shifters 64 Switches 64 Output Output V0 V8 18 Low Voltage High Voltage 3.Digital Source Driver Power Arrangement AVDD a VSS c d e b a b c d e f f VDD VSS Vin Vout 4.DAC Decoder all working at high voltage AVDD VSS c d e a

29、b Timing control f VDD VSS Vin Vout Low Voltage High Voltage 4.DAC Decoder combine LV&HV Cont.Level Shifter Range I DAC I Level Shifter Range II DAC II Input digital code Higher voltage path Lower voltage path Level Shifter Range I DAC I Level Shifter Range II DAC II Input digital code Higher voltag

30、e path Lower voltage path Without Buffer With Buffer 5.DAC Output Structure Level Shifter Range I DAC I Level Shifter Range II DAC II Input digital code 1 Higher voltage path Lower voltage path Input digital code 2 Channel 1 Channel 2 5.Two Output Channels Share HV&LV path Cont.Level Shifter Range I

31、 DAC I Level Shifter Range II DAC II S/H I Buffer Output I Input digital code Higher voltage path Lower voltage path Output S/H II EN H EN L 6.High Voltage Operation with LV Process VSS VDD Vshld Vin VSS Vshld G S D Vshld G D S High Voltage Shielding Device Cont.VSS2 Upper Voltage Range Lower Voltag

32、e Range DAC I DAC II ENH ENL OUTPUT Figure 2 Buffer Output I VDD1 High Voltage Shielding DAC Output Cont.D/A converter 1 D/A converter 2 D/A converter 16 D/A converter 15 Vmiddle Pload chip internal 7.Charge Conservation Block Diagram Charge Sharing Cstore Output N Ctrl Charge Conservation Timing Cont.Discussion