德州仪器POE芯片TPS23785B具有绿色环保模式的高功耗、.pdf

《德州仪器POE芯片TPS23785B具有绿色环保模式的高功耗、.pdf》由会员分享，可在线阅读，更多相关《德州仪器POE芯片TPS23785B具有绿色环保模式的高功耗、.pdf（47页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、TPS23785BM1RCSDVC1GATERTNVCCSCVCCTL58V0.1uFRDENFrom EthernetPairs 1,2VSSCINFrom Ethernet Pairs 3,4CLSDENFRST2PRCLSType 2 PSE IndicatorRFRSVBCVBRFBURFBLTLV431CIZVOUTPADVDDGAT2M2RT2PDARAPD2RAPD1AdapterRCTLAPDCOUTT1RVCARTNNCVDD1COMRBLNKBLNKDTRDTTPS23785BZHCSAN5A DECEMBER 2012REVISED DECEMBER 2012高高功功率率

2、、高高效效 PoE 受受电电设设备备(PD)和和 DC 至至 DC 控控制制器器1特特性性说说明明2功功率率高高达达 30W（输输入入）PDTPS23785B 是一款将以太网供电(PoE)受电设备(PD)接口与电流模式 DC 至 DC 控制器（针对非隔离针针对对非非隔隔离离转转换换器器对对 DC 至至 DC 控控制制进进行行了了优优化化转换器进行了优化）组合在一起的器件。此 PoE 接口支支持持高高效效拓拓扑扑结结构构支持 IEEE 802.3at 标准。完完整整的的 PoE 接接口口符符合合 IEEE 802.3at 标标准准且且具具有有状状态态标标志志的的增增强强型型TPS23785B 支

3、持一定数量的输入电压 ORing 选项，分分类类其中包括最高电压、外部适配器基准和 PoE 优先选适适配配器器或或运运算算(ORing)支支持持择。这些特性使得设计人员能够确定哪个电源在所有稳稳定定耐耐用用的的 100V，0.5 热热插插拔拔金金属属氧氧化化物物半半导导体体情况下来承担负载。场场效效应应晶晶体体管管(MOSFET)PoE 接口特有与高功率中跨式供电设备(PSE)（符合-40C 至至 125C 的的工工作作结结点点温温范范围围IEEE 802.3at 标准）兼容所需的两事件、物理层分行行业业标标准准 PowerPAD 薄薄型型小小外外形形尺尺寸寸(TSSOP)-24 封封装装类。

4、签名检测引脚也可被用来强制关闭 PoE 供电。使用一个单个电阻器可将分类设定为已定义类别中的任应应用用范范围围何一个。IEEE 802.3at 兼兼容容器器件件视视频频和和网网络络语语音音(VoIP)电电话话RFID 阅阅读读器器监监控控摄摄像像机机无无线线访访问问点点设设备备典典型型应应用用图图1Please be aware that an important notice concerning availability,standard warranty,and use in critical applications ofTexas Instruments semiconductor

5、products and disclaimers thereto appears at the end of this data sheet.2PowerPAD is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.版权 2012,Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard w

6、arranty.Production processing does notEnglish Data Sheet:SLUSB90necessarily include testing of all parameters.TPS23785BZHCSAN5A DECEMBER 2012REVISED DECEMBER 说说明明（续续）DC 至 DC 控制器特有两个支持可编程死区时间的互补栅极驱动器。这样简化了采用次级同步整流的高效反激式拓扑结构的设计。如果需要单一 MOSFET 拓扑，可将第二栅极驱动器禁用。此控制器还特有内部软启动、引导加载程序启动源、电流模式补偿和一个最大值为 78%的占空比。

7、一个可编程和可同步振荡器可针对使用效率对设计进行优化并简化控制器的使用以升级现有的电源设计。具有一个缺省周期的精确可编程消隐简化了常见电流感测滤波器设计平衡。This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled withappropriate precautions.Failure to observe proper handling and installation procedures can cause damag

8、e.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.PRODUCT INFORMATION(1)POE UVLOCONVERTER UVLODUTY

9、CYCLEON/HYST.ON/HYST.PACKAGEMARKING(V)(V)TPS23785BPWP078%35/4.515/6.5TSSOP-24 PowerPADTPS23785B(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or consult yourTI salesperson.ABSOLUTE MAXIMUM RATINGS(1)(2)Voltage with respect to VSSu

10、nless otherwise noted.Over recommended operating junction temperature range.VALUEUNITARTN(2),COM(2),DEN,RTN(3),VDD,VDD10.3 to 100CLS(4)-0.3 to 6.5APD,BLNK(4),CTL,DT(4),FRS(4),VB(4)to ARTN,0.3 to 6.5COMInput voltage rangeP1,P2(4)to ARTN,COM0.3 to 6.5VCS to ARTN,COM0.3 to VBARTN,COM to RTN2 to 2T2P(4)

11、,VCto ARTN,COM0.3 to 19Voltage rangeGATE(4),GAT2(4)to ARTN,COM0.3 to VC+0.3RTNInternally limitedSinking currentT2P20mASourcing currentVBInternally limitedAverage Sourcing orGATE,GAT225mARMSsinking currentHuman body model(HBM)2kVESD ratingCharged device model(CDM)500VMachine model(MM)50ESD system lev

12、el(contact/air)at RJ-45(5)8/15kVOperating junction temperature range,TJ40 to Internally limitedC(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratingsonly and functional operation of the device at these or any other conditions

13、 beyond those indicated under recommended operatingconditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)ARTN and COM tied to RTN.(3)IRTN=0 for VRTN 80V.(4)Do not apply voltage to these pins(5)ESD per EN61000-4-2.A power supply

14、containing the TPS23785B was subjected to the highest test levels in the standard.2Copyright 2012,Texas Instruments IncorporatedTPS23785BZHCSAN5A DECEMBER 2012REVISED DECEMBER 2012RECOMMENDED OPERATING CONDITIONS(1)Voltage with respect to VSS(unless otherwise noted)MINNOMMAXUNITARTN,COM,RTN,VDD,VDD1

15、057T2P(2),VCto ARTN,COM018Input voltage rangeVAPD,CTL,DT,FRS(3),P1,P2 to ARTN,COM0VBCS to ARTN,COM02Sinking currentT2P2Continuous RTN current(TJ 125C)(4)825mASourcing currentVB02.55CapacitanceVB0.08FRBLNK0350kSynchronization pulse width input(when used)25nsOperating junction temperature range,TJ4012

16、5C(1)ARTN and COM tied to RTN.(2)T2P current is limited.(3)Pulse voltage applied for synchronization.(4)This is the minimum current-limit value.Viable systems will be designed for maximum currents below this value with reasonable margin.IEEE 802.3at permits 600mA continuous loading.THERMAL INFORMATI

17、ONTPS23785BTHERMAL METRIC(1)TSSOPUNITS24 PINSJAJunction-to-ambient thermal resistance(2)32.6JCtopJunction-to-case(top)thermal resistance(3)16.9JBJunction-to-board thermal resistance(4)17.9C/WJTJunction-to-top characterization parameter(5)0.2JBJunction-to-board characterization parameter(6)7.4JCbotJu

18、nction-to-case(bottom)thermal resistance(7)1.8(1)有关传统和新的热 度量的更多信息，请参阅IC封装热度量应用报告，SPRA953。(2)在 JESD51-2a 描述的环境中，按照 JESD51-7 的指定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然 对流条件下的结至环境热阻。(3)通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。不存在特定的 JEDEC 标准测试，但 可在 ANSI SEMI 标准 G30-88 中能找到内容接近的说明。(4)按照 JESD51-8 中的说明，通过 在配有用于控制 PCB 温度的

19、环形冷板夹具的环境中进行仿真，以获得结板热阻。(5)结至顶部特征参数，JT，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该参数以便获得 JA。(6)结至电路板特征参数，JB，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该参数以便获得 JA。(7)通过在外露（电源）焊盘上进行冷板测试仿真来获得 结至芯片外壳（底部）热阻。不存在特定的 JEDEC 标准 测试，但可在 ANSI SEMI标准 G30-88 中能找到内容接近的说明。空白Copyright 2012,T

20、exas Instruments Incorporated3TPS23785BZHCSAN5A DECEMBER 2012REVISED DECEMBER ELECTRICAL CHARACTERISTICSUnless otherwise noted:CS=COM=APD=CTL=RTN=ARTN,GATE and GAT2 float,RFRS=68.1 k,RBLNK=249 k,DT=VB,T2P open,CVB=CVC=0.1 F,RDEN=24.9 k,RCLSopen,0 V (VDD,VDD1)57 V,0 V VC 18 V,40C TJ 125C.P1=P2=VB.Typ

21、ical specifications are at 25C.CONTROLLER SECTION ONLYVSS=RTN and VDD=VDD1 or VSS=RTN=VDD,all voltages referred to ARTN,COM.PARAMETERTEST CONDITIONSMINTYPMAXUNITVCVCUVVCrising14.31515.7UVLOVVCUVHHysteresis(1)6.26.56.8Operating currentVC=12 V,CTL=VB,RDT=75 k0.740.961.24mAVDD1=19.2 V,VC(0)=0 V4981166B

22、ootstrap startup time,tSTmsCVC=22 FVDD1=35 V,VC(0)=0 V4475158VDD1=19.2 V,VC=13.9 V1.73.45.5Startup current source-IVCmAVDD1=48 V,VC=0 V2.74.86.8VBVoltage6.5 V VC 18 V,0 IVB 5 mA4.85.105.25VFRSCTL=VB,measure GATESwitching frequencykHzRFRS=68.1 k227253278DMAXDuty cycleCTL=VB,measure GATE76%78%80%VSYNC

23、SynchronizationInput threshold22.22.4VCTLVZDC0%duty cycle thresholdVCTL until GATE stops1.31.51.7VSoftstart periodInterval from switching start to VCSMAX1.93.96.2msInput resistance70100145kBLNKBLNK=RTN355578Blanking delayns(In addition to t1)RBLNK=49.9 k385570DTCTL=VB,CGATE=1 nF,CGAT2=1 nF,measure G

24、ATE,GAT2tDT1RDT=24.9 k,GAT2 to GATE 405062.5Dead timenstDT2See Figure 1 for tDTxdefinitionRDT=24.9 k,GATE to GAT2 405062.5tDT1RDT=75 k,GAT2 to GATE 120150188tDT2RDT=75 k,GATE to GAT2 120150188(1)The hysteresis tolerance tracks the rising threshold for a given device.4Copyright 2012,Texas Instruments

25、 IncorporatedTPS23785BZHCSAN5A DECEMBER 2012REVISED DECEMBER 2012PARAMETERTEST CONDITIONSMINTYPMAXUNITCSVCSMAXMaximum threshold voltageVCTL=VB,VCSrising until GATE duty cycle drops0.50.550.6Vt1Turnoff delayVCS=0.65 V244070nsPeak voltage at maximum duty cycle,referencedVSLOPEInternal slope compensati

26、on voltage120155185mVto CSISL_EXPeak slope compensation currentVCTL=VB,ICSat maximum duty cycle304254ABias current(sourcing)DC component of ICS12.54.3GATEVCTL=VB,VC=12 V,GATE high,pulsedSource current0.370.60.95measurementAVCTL=VB,VC=12 V,GATE low,pulsedSink current0.711.4measurementGAT2VCTL=VB,VC=1

27、2 V,GAT2 high,RDT=24.9 k,Source current0.370.60.95pulsed measurementAVCTL=VB,VC=12 V,GAT2 low,RDT=24.9 k,Sink current0.711.4pulsed measurementAPDVAPDENVAPDrising1.431.51.57APD threshold voltageVVAPDHHysteresis(2)0.290.310.33APD leakage currentVC=12 V,VAPD=VB1A(source or sink)P1,P2Leakage currentSour

28、ce or sink1A(2)The hysteresis tolerance tracks the rising threshold for a given device.Copyright 2012,Texas Instruments Incorporated5TPS23785BZHCSAN5A DECEMBER 2012REVISED DECEMBER ELECTRICAL CHARACTERISTICS PoE AND CONTROLVDD=VDD1 or VDD1=RTN,VC=RTN,COM=RTN=ARTN,all voltages referred to VSSunless o

29、therwise notedPARAMETERTEST CONDITIONSMINTYPMAXUNITDETECTION(DEN)(VDD=VDD1=RTN=VSUPPLYpositive)Measure ISUPPLYDetection currentVDD=1.6 V6264.366.5AVDD=10 V399406414VDD=10 V,float DEN,measure ISUPPLY,Detection bias current5.610ANote:Not during Mark stateVPD_DISHotswap disable threshold345VDEN leakage

30、 currentVDEN=VDD=57 V,float VDD1and RTN,measure IDEN0.15ACLASSIFICATION(CLS)(VDD=VDD1=RTN=VSUPPLYpositive)13 V VDD 21 V,Measure ISUPPLYRCLS=1270 (Class 0)1.82.12.4RCLS=243 (Class 1)9.910.410.9Classification current,ICLSmAapplies to both cyclesRCLS=137 (Class 2)17.618.519.4RCLS=90.9 (Class 3)26.527.7

31、29.3RCLS=63.4 (Class 4)3839.742Classification mark resistance5.6 V VDD 9.4 V7.59.712kVCL_ONRegulator turns on,VDDrising11.211.912.6Classification regulator lowerVthresholdVCL_HHysteresis(1)1.551.651.75VCU_OFFRegulator turns off,VDDrising212223Classification regulator upperVthresholdVCU_HHysteresis(1

32、)0.50.751VMSRMark state resetVDDfalling345VLeakage currentVDD=57 V,VCLS=0 V,DEN=VSS,measure ICLS1APASS DEVICE(RTN)(VDD1=RTN)On resistance0.250.430.75Current limitVRTN=1.5 V,VDD=48 V,pulsed measurement8509701100mAInrush limitVRTN=2 V,VDD:0 V 48 V,pulsed measurement100140180mAFoldback voltage threshol

33、dVDDrising1112.313.6VUVLOVUVLO_RVDDrising33.93536.1UVLO thresholdVVUVLO_HHysteresis(1)4.44.554.76T2PPerform classification algorithm,VT2P-RTN=1 V,ON characteristic2mACTL=ARTNLeakage currentVT2P=18 V,CTL=VB10AtT2PDelayFrom start of switching to T2P active5915msTHERMAL SHUTDOWNTurnoff temperatureTJris

34、ing135145155CHysteresis(2)20C(1)The hysteresis tolerance tracks the rising threshold for a given device.(2)These parameters are specified by design and are not production tested.6Copyright 2012,Texas Instruments Incorporated12345671514131112816VDDDENDTFRSCLSGATERTNVCCSVSS(pad)VBCTLT2PBLNKGAT21091918

35、1720APDARTNVDD1N/CCOM21222324N/CP1P2N/C=Leave Pin UnusedThermal PadPAD=VSSN/CTPS28785BPWP PACKAGE(TOP VIEW)tDT1GATEGAT250%50%tDT2timelolohihiTPS23785BZHCSAN5A DECEMBER 2012REVISED DECEMBER 2012Timing DiagramFigure 1.GATE and GAT2 Timing and Phasing DiagramDEVICE INFORMATIONCopyright 2012,Texas Instr

36、uments Incorporated7DCLRBQOscillator1GATEVDD1RegVCVBRefCTLFRSControlenbCONV.OFF+-3.9msSoftstart0.55V-+-CK11.9V&10.3V22V&21.25V35V&30.5VClassLogic&RegulatorVDD50mW10SRQ12.3VILIMHLVSSCommonCircuits andPoE ThermalMonitorRTNCLSAPDVSSDEN+-400msEN2.5VCONV.OFF4V1.5V&1.2VARTN+0.75VGAT2DTCOMARTNT2PARTNsaARTN

37、ConverterThermalMonitorffsst2T2StateEng.t24Vpa,sa,denCTLfDeadtimeGlobal Cvtr.Enable50kW50kWBLNKARTNCS42mA(pk)3.69kWenbHotswapMOSFETSwitchMatrixT2P Logicfpddenuvlouvlo,fpduvloTPS23785BZHCSAN5A DECEMBER 2012REVISED DECEMBER Functional Block Diagram8Copyright 2012,Texas Instruments IncorporatedTPS23785

38、BZHCSAN5A DECEMBER 2012REVISED DECEMBER 2012PIN FUNCTIONSNAMEPINTYPEDESCRIPTIONP11ITie this pin to VB.P22ITie this pin to VB.CTL3IThis is the control loop input to the PWM(pulse width modulator),typically driven by output regulationfeedback(e.g.optocoupler).Use VBas a pullup for CTL.VB4O5.1 V bias r

39、ail for dc/dc control circuits and the feedback optocoupler.Typically bypass with a 0.1 F toARTN.CS5I/ODC/DC converter switching MOSFET current sense input.See RCSin the 典型应用图.COM6Gate driver return,connect to ARTN and RTN.GATE7OGate drive output for the main dc/dc converter switching MOSFET.VC8I/OD

40、C/DC converter bias voltage.Connect a 0.47 F(minimum)ceramic capacitor to ARTN at the pin,and alarger capacitor to power startup.GAT29OGate drive output for a second dc/dc converter switching MOSFET.ARTN10ARTN is the dc/dc converter analog return.Tie to RTN and COM on the circuit board.RTN11RTN is t

41、he output of the PoE hotswap MOSFET.VSS12Connect to the negative power rail derived from the PoE source.VDD113ISource of dc/dc converter startup current.Connect to VDDfor many applications.VDD14IConnect to the positive PoE input power rail.VDDpowers the PoE interface circuits.Bypass with a 0.1 Fcapa

42、citor and protect with a TVS.DEN15I/OConnect a 24.9 k resistor from DEN to VDDto provide the PoE detection signature.Pulling this pin to VSSduring powered operation causes the internal hotswap MOSFET to turn off.N/C16Do not connect this pin.CLS17IConnect a resistor from CLS to VSSto program classifi

43、cation current.2.5 V is applied to the program resistorduring classification to set class current.DT18IConnect a resistor from DT to ARTN to set the GATE to GAT2 dead time.Tie DT to VBto disable GAT2operation.APD19IRaising VAPD-VARTNabove 1.5 V disables the internal hotswap switch,turns class off,an

44、d forces T2P active.This forces power to come from a external VDD1-RTNadapter.Tie APD to ARTN when not used.BLNK20IConnect to ARTN to utilize the internally set current-sense blanking period,or connect a resistor from BLNKto ARTN to program a more accurate period.FRS21IConnect a resistor from FRS to

45、 ARTN to program the converter switching frequency.FRS may be used tosynchronize the converter to an external timing source.T2P22OActive low output that indicates a PSE has performed the IEEE 802.3at type 2 hardware classification,orAPD is active.T2P pulls current to ARTNN/C23Do not connect this pin

46、.N/C24Do not connect this pin.PadConnect to VSS.Copyright 2012,Texas Instruments Incorporated9()()BLNKBLNKRk=tnsW()()APD1APD2ADPTR_ONAPDENAPDENAPD1APD2ADPTR_OFFAPDENAPDHAPD2R=RVVVR+RV=VVR-TPS23785BZHCSAN5A DECEMBER 2012REVISED DECEMBER Detailed Pin DescriptionSee the 典型应用图 for component reference de

47、signators(RCSfor example),and the Electrical Characteristicstable for values denoted by reference(VCSMAXfor example).Electrical Characteristic values take precedenceover any numerical values used in the following sections.APDAPD forces power to come from an external adapter connected from VDD1to RTN

48、 by opening the hotswapswitch,disabling the CLS output,and enabling the T2P output.A resistor divider is recommended on APD whenit is connected to an external adapter.The divider provides ESD protection,leakage discharge for the adapterORing diode,and input voltage qualification.Voltage qualificatio

49、n assures the adapter output voltage is highenough that it can support the PD before the PoE current is cut off.Select the APD divider resistors per Equation 1 where VADPTR-ONis the desired adapter voltage that enables theAPD function as adapter voltage rises.(1)SLVA306A(or most recent)provides a sa

50、mple calculation.Place the APD pull-down resistor adjacent to the APD pin.APD should be tied to ARTN when not used.BLNKBlanking provides an interval between GATE going high and the current-control comparators on CS activelymonitoring the input.This delay allows the normal turn-on current transient(s