[主板]主板系统时钟W229B芯片电路图.pdf

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1、Frequency Generator for Integrated Core Logicwith 133-MHz FSBW229B Cypress Semiconductor Corporation3901 North First StreetSan JoseCA 95134408-943-2600Document#:38-07223 Rev.*A Revised December 21,2002Features Maximized EMI suppression using Cypresss Spread Spectrum technology Low jitter and tightly

2、 controlled clock skew Highly integrated device providing clocks required for CPU,core logic,and SDRAM Two copies of CPU clock Thirteen copies of SDRAM clock Eight copies of PCI clock One copy of synchronous APIC clock Three copies of 66-MHz outputs Two copies of 48-MHz outputs One copy of selectabl

3、e 24-or 48-MHz clock One copy of double strength 14.31818-MHz reference clock Power-down control SMBus interface for turning off unused clocksKey SpecificationsCPU,SDRAM Outputs Cycle-to-Cycle Jitter:.250 psAPIC,48-MHz,3V66,PCI Outputs Cycle-to-Cycle Jitter:.500 psCPU,3V66 Output Skew:.175 psSDRAM,A

4、PIC,48-MHz Output Skew:.250 psPCI Output Skew:.500 psCPU to SDRAM Skew(133 MHz).0.5 nsCPU to SDRAM Skew(100 MHz).4.5 to 5.5 nsCPU to 3V66 Skew(66 MHz).7.0 to 8.0 ns3V66 to PCI Skew(3V66 lead).1.5 to 3.5 nsPCI to APIC Skew.0.5 ns Table 1.Frequency Selections FS4 FS3 FS2 FS1 FS0CPUSDRAM3V66PCIAPICSS00

5、00075.3113.075.337.618.8OFF0000195.095.063.331.615.80.6%00010129.0129.086.043.021.5OFF00011150.0113.075.337.618.8OFF00100150.0150.075.037.518.7OFF00101110.0110.073.036.618.3OFF00110140.0140.070.035.017.5OFF00111144.0108.072.036.018.0OFF0100068.3102.568.334.117.0OFF01001105.0105.070.035.017.5OFF01010

6、138.0138.069.034.517.0OFF01011140.0105.070.035.017.5OFF0110066.8100.266.833.416.70.45%01101100.2100.266.833.416.70.45%01110133.6133.666.833.416.70.45%01111133.6100.266.833.416.70.45%10000157.3118.078.639.319.6OFF10001160.0120.080.040.020.0OFF10010146.6110.073.336.618.3OFF10011122.091.561.030.515.20.

7、6%10100127.0127.084.642.321.1OFF10101122.0122.081.340.620.30.6%10110117.0117.078.039.019.5OFF10111114.0114.076.038.019.0OFF1100080.0120.080.040.020.0OFF1100178.0117.078.039.019.5OFF11010166.0124.583.041.520.7OFF11011133.6133.689.044.522.2OFF1110066.6100.066.633.316.60.6%11101100.0100.066.633.316.60.

8、6%11110133.3133.366.633.316.60.6%11111133.3100.066.633.316.60.6%Block DiagramPin ConfigurationNote:1.Internal pull-down or pull-up resistors present on inputs marked with*or,respectively.Design should not rely solely on internal pull-up or pull-down resistor to set I/O pins HIGH or LOW,respectively.

9、1VDDQ3VDDQ2PCI1/FS1*XTAL PLL REF FREQPLL 1X2X1REF2X/FS3*PCI3:748MHz_1/FS4*SI0/24_48 MHz#*PLL2OSCVDDQ3I2CSDATALogicSCLK 3V66_0:2CPU0:1APICDivider,Delay,and Phase Control Logic3VDDQ32SDRAM0:1213PWRDWN#PCI0/FS0*PCI2/FS2*/2(FS0:4*)548MHz_0GNDVDDQ3REF2X/FS3*X1X2VDDQ33V66_03V66_13V66_2GNDPCI0/FS0*PCI1/FS1

10、*PCI2/FS2*GNDPCI3PCI4VDDQ3PCI5PCI6PCI7GND48MHz_048MHz_1/FS4*SIO/24_48MHz#*W229BVDDQ2APICGNDVDDQ2CPU0CPU1GNDSDRAM0SDRAM1SDRAM2VDDQ3GNDSDRAM3SDRAM4SDRAM5SDRAM6VDDQ3GNDSDRAM7SDRAM8SDRAM9SDRAM10VDDQ3GND565554535251504948474645444342414039383736353433123456789101112131415161718192021222324252627283231302

11、9VDDQ3SDATAGNDVDD3SDRAM11SDRAM12PWRDWN#SCLKW229B Document#:38-07223 Rev.*APage 2 of 17IPin DefinitionsPin NamePin No.Pin TypePin DescriptionREF2x/FS3*3I/OReference Clock with 2x Drive/Frequency Select 3:3.3V 14.318-MHz clock out-put.This pin also serves as the select strap to determine device operat

12、ing frequency as described in Table 1.X14ICrystal Input:This pin has dual functions.It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input.X25ICrystal Output:An input connection for an external 14.318-MHz crystal connec-tion.If using an external refer

13、ence,this pin must be left unconnected.PCI0/FS0*11I/OPCI Clock 0/Frequency Selection 0:3.3V 33-MHz PCI clock outputs.This pin also serves as the select strap to determine device operating frequency as described in Table 1.PCI1/FS1*12I/OPCI Clock 1/Frequency Selection 1:3.3V 33-MHz PCI clock outputs.

14、This pin also serves as the select strap to determine device operating frequency as described in Table 1.PCI2/FS2*13I/OPCI Clock 2/Frequency Selection 2:3.3V 33-MHz PCI clock outputs.This pin also serves as the select strap to determine device operating frequency as described in Table 1.PCI3:715,16,

15、18,19,20OPCI Clock 3 through 7:3.3V 33-MHz PCI clock outputs.PCI0:7 can be individually turned off via SMBus interface.3V66_0:27,8,9O66-MHz Clock Output:3.3V output clocks.The operating frequency is controlled by FS0:4(see Table 1).48MHz_022O48-MHz Clock Output:3.3V fixed 48-MHz,non-spread spectrum

16、clock output.48MHz_1/FS4*23I/O48-MHz Clock Output/Frequency Selection 4:3.3V fixed 48-MHz,non-spread spectrum clock output.This pin also serves as the select strap to determine device operating frequency as described in Table 1.SIO/24_48MHz#*24I/OClock Output for Super I/O:This is the input clock fo

17、r a Super I/O(SIO)device.During power up,it also serves as a selection strap.If it is sampled HIGH,the output frequency for SIO is 24 MHz.If the input is sampled LOW,the output is 48 MHz.PWRDWN#30IPower Down Control:LVTTL-compatible input that places the device in power-down mode when held LOW.CPU0:

18、152,51OCPU Clock Outputs:Clock outputs for the host bus interface.Output frequencies depending on the configuration of FS0:4.Voltage swing is set by VDDQ2.SDRAM0:12,49,48,47,44,43,42,41,38,37,36,35,32,31OSDRAM Clock Outputs:3.3V outputs for SDRAM and chipset.The operating fre-quency is controlled by

19、 FS0:4(see Table 1).APIC55OSynchronous APIC Clock Outputs:Clock outputs running synchronous with the PCI clock outputs.Voltage swing set by VDDQ2.SDATA26I/OData pin for SMBus circuitry.SCLK29IClock pin for SMBus circuitry.VDDQ32,6,17,25,34,40,46P3.3V Power Connection:Power supply for SDRAM output bu

20、ffers,PCI output buff-ers,reference output buffers and 48-MHz output buffers.Connect to 3.3V.VDD328P3.3V Power Connection:Power supply for PLL core.VDDQ253,56P2.5V Power Connection:Power supply for IOAPIC and CPU output buffers.Con-nect to 2.5V or 3.3V.GND1,10,14,21,27,33,39,45,50,54GGround Connecti

21、ons:Connect all ground pins to the common system ground plane.W229B Document#:38-07223 Rev.*APage 3 of 17OverviewThe W229B is a highly integrated frequency timing generator,supplying all the required clock sources for an Intel architec-ture platform using graphics integrated core logic.Functional De

22、scriptionI/O Pin OperationPin#3,11,12,13,23,and 24 are dual-purpose l/O pins.Uponpower-up the pin acts as a logic input.An external 10-k strap-ping resistor should be used.Figure 1 shows a suggestedmethod for strapping resistor connections.After 2 ms,the pin becomes an output.Assuming the powersuppl

23、y has stabilized by then,the specified output frequencyis delivered on the pins.If the power supply has not yetreached full value,output frequency initially may be below tar-get but will increase to target once supply voltage has stabi-lized.In either case,a short output clock cycle may be pro-duced

24、 from the CPU clock outputs when the outputs areenabled.Offsets Among Clock Signal GroupsFigure 2,Figure 3,and Figure 4 represent the phase relation-ship among the different groups of clock outputs from W229Bwhen it is providing a 66-MHz CPU clock,a 100-MHz CPUclock,and a 133-MHz CPU clock,respectiv

25、ely.It should benoted that when CPU clock is operating at 100 MHz,CPUclock output is 180 degrees out of phase with SDRAM clockoutputs.Power Down ControlW229B provides one PWRDWN#signal to place the device inlow-power mode.In low-power mode,the PLLs are turned offand all clock outputs are driven LOW.

26、Power-onResetTimerOutput Three-stateDataLatchHoldQDW229BClock LoadOutputBuffer10 kOutputLow Output Strapping ResistorSeries Termination ResistorFigure 1.Input Logic Selection Through Resistor Load Option.CPU 66-MHzSDRAM 100-MHz3V66 66-MHzPCI 33-MHzREF 14.318-MHzUSB 48-MHzAPIC 0 ns Figure 2.Group Off

27、set Waveforms(66-MHz CPU Clock,100-MHz SDRAM Clock).40 ns30 ns20 ns10 nsSDRAM 100 PeriodCPU 100 PeriodHub-PCW229B Document#:38-07223 Rev.*APage 4 of 17CPU 100-MHzSDRAM 100-MHz3V66 66-MHzPCI 33-MHzREF 14.318-MHzUSB 48-MHzAPIC0 nsFigure 3.Group Offset Waveforms(100-MHz CPU Clock/100-MHz SDRAM Clock).4

28、0 ns30 ns20 ns10 nsSDRAM 100 PeriodCPU 100 PeriodHub-PCCPU 133-MHzSDRAM 100-MHz3V66 66-MHzPCI 33-MHzREF 14.318-MHzUSB 48-MHzDOT 48-MHzCycle RepeatsAPIC 33-MHzFigure 4.Group Offset Waveforms(133-MHz CPU/100-MHz SDRAM).0 ns40 ns30 ns20 ns10 nsW229B Document#:38-07223 Rev.*APage 5 of 17Notes:2.Once the

29、 PWRDWN#signal is sampled LOW for two consecutive rising edges of CPU,clocks of interest will be held LOW on the next HIGH-to-LOW transition.3.PWRDWN#is an asynchronous input and metastable conditions could exist.This signal is synchronized inside W229B.4.The shaded sections on the SDRAM,REF,and USB

30、 clocks indicate“Dont Care”states.5.Diagrams shown with respect to 100 MHz.Similar operation when CPU is 66 MHz.CPU 100-MHzSDRAM 133-MHz3V66 66-MHzPCI 33-MHzREF 14.318-MHzUSB 48-MHzDOT 48-MHzAPIC 33-MHzCycle RepeatFigure 5.Group Offset Waveform(133-MHz CPU/133-MHz SDRAM).0 ns40 ns30 ns20 ns10 ns12Ce

31、nter0ns25ns50ns75nsVCO InternalCPU 100MHz3V66 66MHzPCI 33MHzAPIC 33MHzPwrDwnSDRAM 100MHzREF 14.318MHzUSB 48MHzFigure 6.W229B PWRDWN#Timing Diagram2,3,4,5.W229B Document#:38-07223 Rev.*APage 6 of 17Table 2.W229B Maximum Allowed Current W229B ConditionMax 2.5V supply consumptionMax discrete cap loads,

32、VDDQ2=2.625VAll static inputs=VDDQ3 or VSSMax 3.3V supply consumption Max discrete cap loadsVDDQ3=3.465VAll static inputs=VDDQ3 or VSSFull Active 66 MHzFSEL4:0=01100(PWRDWN#=1)70 mA280 mAFull Active 100 MHzFSEL4:0=11101(PWRDWN#=1)100 mA280 mAFull Active 133 MHzFSEL4:0=11110(PWRDWN#=1)50 mA400 mAW229

33、B Document#:38-07223 Rev.*APage 7 of 17Spread Spectrum Frequency Timing GeneratorThe device generates a clock that is frequency modulated inorder to increase the bandwidth that it occupies.By increasingthe bandwidth of the fundamental and its harmonics,the am-plitudes of the radiated electromagnetic

34、 emissions are re-duced.This effect is depicted in Figure 7.As shown in Figure 7,a harmonic of a modulated clock has amuch lower amplitude than that of an unmodulated signal.Thereduction in amplitude is dependent on the harmonic numberand the frequency deviation or spread.The equation for thereducti

35、on isdB=6.5+9*log10(P)+9*log10(F)Where P is the percentage of deviation and F is the frequencyin MHz where the reduction is measured.The output clock is modulated with a waveform depicted inFigure 8.This waveform,as discussed in“Spread SpectrumClock Generation for the Reduction of Radiated Emissions

36、”byBush,Fessler,and Hardin,produces the maximum reductionin the amplitude of radiated electromagnetic emissions.Thedeviation selected for this chip is 0.45%or-0.6%of the se-lected frequency.Figure 7 details the Cypress spreading pat-tern.Cypress does offer options with more spread and greaterEMI red

37、uction.Contact your local Sales representative for de-tails on these devices.SSFTGTypical ClockFrequency Span(MHz)Center SpreadAmplitude(dB)SpreadSpectrumEnabledEMI ReductionSpreadSpectrumNon-Frequency Span(MHz)Down SpreadAmplitude(dB)Figure 7.Clock Harmonic with and without SSCG Modulation Frequenc

38、y Domain Representa-tion.MAX.MIN.10%20%30%40%50%60%70%80%90%100%10%20%30%40%50%60%70%80%90%100%FREQUENCYFigure 8.Typical Modulation Profile.W229B Document#:38-07223 Rev.*APage 8 of 17Serial Data InterfaceThe W229B features a two-pin,serial data interface that canbe used to configure internal registe

39、r settings that control par-ticular device functions.Data ProtocolThe clock driver serial protocol accepts only block writes fromthe controller.The bytes must be accessed in sequential orderfrom lowest to highest byte with the ability to stop after anycomplete byte has been transferred.Indexed bytes

40、 are notallowed.A block write begins with a slave address and a write condition.After the command code the core logic issues a byte countwhich describes how many more bytes will follow in the mes-sage.If the host had 20 bytes to send,the first byte would bethe number 20(14h),followed by the 20 bytes

41、 of data.Thebyte count may not be 0.A block write command is allowed totransfer a maximum of 32 data bytes.The slave receiver ad-dress for W229B is 11010010.Figure 9 shows an example ofa block write.The command code and the byte count bytes are required asthe first two bytes of any transfer.W229B ex

42、pects a commandcode of 0000 0000.The byte count byte is the number of ad-ditional bytes required for the transfer,not counting the com-mand code and byte count bytes.Additionally,the byte countbyte is required to be a minimum of 1 byte and a maximum of32 bytes to satisfy the above requirement.Table

43、3 shows anexample of a possible byte count value.A transfer is considered valid after the acknowledge bit corre-sponding to the byte count is read by the controller.The com-mand code and byte count bytes are ignored by the W229B.However,these bytes must be included in the data write se-quence to mai

44、ntain proper byte allocation.Notes:6.The acknowledgment bit is returned by the slave/receiver(W229B).7.Bytes 6 and 7 are not defined for W229B.1 bit7 bits118 bits1Start bitSlave AddressR/WAckCommand CodeAckByte Count=NAckData Byte 1AckData Byte 2Ack.Data Byte NAckStop1 bit8 bits18 bits18 bits1 1Figu

45、re 9.An Example of a Block Write6.Table 3.Example of Possible Byte Count Value Byte Count ByteNotesMSBLSB00000000Not allowed.Must have at least one byte.00000001Data for functional and frequency select register(currently byte 0 in spec)00000010Reads first two bytes of data.(byte 0 then byte 1)000000

46、11Reads first three bytes(byte 0,1,2 in order)00000100Reads first four bytes(byte 0,1,2,3 in order)00000101Reads first five bytes(byte 0,1,2,3,4 in order)700000110Reads first six bytes(byte 0,1,2,3,4,5 in order)700000111Reads first seven bytes(byte 0,1,2,3,4,5,6 in order)00100000Max.byte count suppo

47、rted=32Table 4.Serial Data Interface Control Functions Summary Control FunctionDescriptionCommon ApplicationOutput DisableAny individual clock output(s)can be disabled.Disabled outputs are actively held LOW.Unused outputs are disabled to reduce EMI and sys-tem power.Examples are clock outputs to unu

48、sed PCI slots.(Reserved)Reserved function for future device revision or pro-duction device testing.No user application.Register bit must be written as 0.W229B Document#:38-07223 Rev.*APage 9 of 17W229B Serial Configuration Map1.The serial bits will be read by the clock driver in the following order:

49、Byte 0-Bits 7,6,5,4,3,2,1,0Byte 1-Bits 7,6,5,4,3,2,1,0Byte N-Bits 7,6,5,4,3,2,1,02.All unused register bits(reserved and N/A)should be writ-ten to a“0”level.3.All register bits labeled“Initialize to 0 must be written to zero during initialization.Failure to do so may result in high-er than normal op

50、erating current.The controller will read back the written value.Note:8.Inactive means outputs are held LOW and are disabled from switching.These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation.Byte 0:Control Register(1=Enab