Synplicity 培训以及试验相关资料(PDF 107).pdf

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1、1Advanced Synthesis with the Synplify ProToolWinter/Spring 20032Course OutlineCourse Outline?Introduction?HDL Coding for PerformanceLab 1?Technology Independent Attributes?Technology Specific AttributesLab 3?Advanced Synthesis Topics for Altera CPLD?Complex Clocking?RetimingLab 2Lab 4Lab 5?Advanced

2、Synthesis Topics for Xilinx FPGA?MultiPoint Synthesis Flow23IntroductionIntroductionIntroduction?Introduction?HDL Coding for Performance4Synplicity s SolutionsSynplicity s SolutionsCertifyAmplifyPhysical OptimizerSynplify Proand SynplifySynplify ASICASICsolutionsFPGAsolutionsbrings leading-edgelogic

3、 synthesisandverificationproductsto FPGAand ASICdesignersSynplicityIntroduction35FPGA Product Line OverviewFPGA Product Line OverviewSynplifyPro ToolChallenging DesignsComplex ProjectsThe Ultimate in FPGA SynthesisSynplify ToolFastEasy to UseExcellent ResultsAmplify Physical Optimizer Physical Synth

4、esis for FPGAsHighest Circuit PerformanceFastest Timing ClosureOption to Synplify ProIntroduction6FPGA Synthesis with the Synplify Pro ToolFPGA Synthesis with the Synplify Pro Tool?Ultra Fast?B.E.S.T.TMalgorithms?Easy to Use?Language sensitive Text Editor?HDL Analysttool?S.C.O.P.E.?Excellent Results

5、?Timing-driven?Direct mapping to technology-specific primitivesIntroductionMarket Leader in FPGA Synthesis47Getting HelpGetting Help?Online Help?Select Help-Help,or F1 function key from the Synplify Pro UI?Synplify Pro User Guide?Pdf file found in/docs?Synplify Pro Reference Guide?Pdf file found in/

6、docs?Synplicity Support?SynplifyOnline SupportSOS and Synplify Newsgroup?http:/ First Level Support?Can be accessed from S.O.S?Send email to ?Call the Technical Support Hotline at(408)215-6000Introduction8HDL Coding for PerformanceHDL Coding for Performance?Introduction?HDL Coding for PerformanceHDL

7、 Coding Techniques for Performance59OverviewOverview?Discuss various HDL coding issues that affect performance?Shared Expressions?Shannon Expansion?Operand Reordering?Priority Encoding?Parallel Case?RAM Inferencing?Other coding issues?Latch Generation?Sensitivity ListHDL Coding Techniques for Perfor

8、mance10Common Boolean ExpressionsCommon Boolean Expressions?Definition?Share identical boolean(sub-)expressions(&,|,)?Pros and Cons?Saves Area?Done automatically?Generally have minimal timing impact?Some situations require source code changes?manual replication?When to use it?Share common expression

9、s to save area(automatic)?Manually replicate expressions to control loading?Large number of loads within a black box?Reduce loading on a critical pathHDL Coding Techniques for Performance611Common Boolean ExpressionsCommon Boolean Expressions?Example?Design details?Goal:meet load restriction of 10?D

10、esign has two black boxes,each with 8 loads on the en input?The Synplify Pro tool does not know about loading within the black boxes?Original Design?a_en and b_en were shared,resulting in 16 loads on en?Fixed Design?Manually forced the a_en and b_en to remain separate?Each enable signal drive only o

11、ne black box(8 loads)HDL Coding Techniques for Performance12Common Boolean ExpressionsCommon Boolean Expressionsmodule bb_load(a1,a2,b1,b2,opcode,clk,rst,a_out,b_out);input clk,rst;input 3:0 opcode;input 7:0 a1,a2,b1,b2;output 7:0 a_out,b_out;reg 7:0 a1_reg,a2_reg,b1_reg,b2_reg;wire 3:0 a_opcode;wir

12、e 3:0 b_opcode;wire a_en;wire b_en;always(posedge clk or negedge rst)if(!rst)begina1_reg=8h00;a2_reg=8h00;b1_reg=8h00;b2_reg=8h00;endelse begina1_reg=a1;a2_reg=a2;b1_reg=b1;b2_reg=b2;endassign a_opcode=opcode;assign b_opcode=opcode;assign a_en=(a_opcode=4b1011)?1b1:1b0;assign b_en=(b_opcode=4b1011)?

13、1b1:1b0;function_a bb_A(a1_reg,a2_reg,a_en,a_out);function_b bb_B(b1_reg,b2_reg,b_en,b_out);endmodulemodule function_a(in1,in2,en,out)/*synthesis syn_black_box*/;input en;input 7:0 in1,in2;output 7:0 out;endmodulemodule function_b(in1,in2,en,out)/*synthesis syn_black_box*/;input en;input 7:0 in1,in2

14、;output 7:0 out;endmodulea_en being shared between function_a and function_b,causing load on it to be(8+8)=16HDL Coding Techniques for Performance713Common Boolean ExpressionsCommon Boolean Expressionsmodule function_a(in1,in2,en,out)/*synthesis syn_black_box*/;input en;input 7:0 in1,in2;output 7:0

15、out;endmodulemodule function_b(in1,in2,en,out)/*synthesis syn_black_box*/;input en;input 7:0 in1,in2;output 7:0 out;endmodulemodule bb_load(a1,a2,b1,b2,opcode,clk,rst,a_out,b_out);input clk,rst;input 3:0 opcode;input 7:0 a1,a2,b1,b2;output 7:0 a_out,b_out;reg 7:0 a1_reg,a2_reg,b1_reg,b2_reg;wire 3:0

16、 a_opcode/*synthesis syn_keep=1*/;wire 3:0 b_opcode/*synthesis syn_keep=1*/;wire a_en;wire b_en;always(posedge clk or negedge rst)if(!rst)begina1_reg=8h00;a2_reg=8h00;b1_reg=8h00;b2_reg=8h00;endelse begina1_reg=a1;a2_reg=a2;b1_reg=b1;b2_reg=b2;endassign a_opcode=opcode;assign b_opcode=opcode;assign

17、a_en=(a_opcode=4b1011)?1b1:1b0;assign b_en=(b_opcode=4b1011)?1b1:1b0;function_a bb_A(a1_reg,a2_reg,a_en,a_out);function_b bb_B(b1_reg,b2_reg,b_en,b_out);endmoduleApplying syn_keep on the signals a_opcode and b_opcode,divide the load on the enable signal to meet the design requirement.HDL Coding Tech

18、niques for Performance14Shannon ExpansionShannon Expansion?Definition?Boolean Transformation?F(a,b,c)=a F(0,b,c)+aF(1,b,c)?Example-F=a b+ac(2 to 1 Mux)?F(a,b,c)=a F(0,b,c)+aF(1,b,c)a(1b+0c)+a(0b+1c)a b+ac?Pros and Cons?Can dramatically improve timing on critical signals?May require substantial chang

19、es in the code?Increases areaHDL Coding Techniques for Performance815Shannon ExpansionShannon Expansion?When to use it?Path is far from meeting timing(25%or more off)?If path is within 20%of the goal,try Synthesis and P&R constraints first.?Critical path has many logic levels?The Synplify Pro tool m

20、ay need to break complex paths limiting its ability to prioritize critical signals.?A small subset of signals have priority?If all signals feeding a cone of logic are equally critical there is no advantage to prioritize one over the other.?Need to move critical signals past an operator?The Synplify

21、Pro tool cannot replicate operators(+,-,*,.)HDL Coding Techniques for Performance16Shannon Expansion ExampleShannon Expansion Example?Design details?65 MHz goal?Signal late has input delay of 8ns?target technology:Actel 54SX Std?Original design?Speed 67.6MHz Area:35 Cells?Fast design(prioritize late

22、 as much as possible-Shannon expansion)?Speed 77.2MHz Area:42 CellsHDL Coding Techniques for Performance917Shannon Expansion ExampleShannon Expansion Examplemodule shannon(in0,in1,in2,late,en,out);input 7:0 in0,in1,in2;input late,en;output out;assign out=(8late|in0)+in1)=in2)&en;endmoduleRequested E

23、stimated Requested Estimated Clock Frequency Frequency Period Period Slack-System 70.0 MHz 67.6 MHz 14.286 14.785 -0.500=Original source-latetraverses an OR gate,an adder,a comparator,and an AND gateHDL Coding Techniques for Performance18Shannon Expansion Example(Cont d)Shannon Expansion Example(Con

24、t d)Requested Estimated Requested Estimated Clock Frequency Frequency Period Period Slack-System 70.0 MHz 77.2 MHz 14.286 12.949 1.337=module shannon_fast(in0,in1,in2,late,en,out);input 7:0 in0,in1,in2;input late,en;output out;wire late_eq_0,late_eq_1;assign late_eq_0=(81b0|in0)+in1)=in2)&en;assign

25、late_eq_1=(81b1|in0)+in1)=in2)&en;assign out=(late)?late_eq_1:late_eq_0;endmoduleRe-coding using Shannon Expansion reduces the number of levels of logic from late to out.HDL Coding Techniques for Performance1019Operand ReorderingOperand Reordering?Definition?Use algebraic identities to prioritize si

26、gnals?“A+B=C”is equivalent to“A=C-B”?Pros and Cons?Can dramatically improve timing on critical signals?Usually no area penalty?Requires minor changes to source code?When to use it?A small subset of signals have priority?Need to move critical signals past an operatorHDL Coding Techniques for Performa

27、nce20Operand ReorderingOperand Reordering?Example?Design Details?54 MHz goal?Signal ADDR has an input delay of 8ns?Target Technology:Lattice ORCAFPSC?Original design?39.9 Mhz?the“late”signal must traverse an adder and a comparator?Speed:39.9 Mhz Area:80 cells?Fast design?Meets timing?the“late”signal

28、 must traverse only the comparator?Speed:54.3 Mhz Area:86 cellsHDL Coding Techniques for Performance1121Lab1Lab1?Go through all the steps in Lab1HDL Coding Techniques for Performance22Technology Independent AttributesTechnology Independent AttributesTechnology Independent Attributes?Technology Indep

29、endent Attributes?Technology Specific Attributes1223Attributes OverviewAttributes Overview?Discuss Technology Independent Attributes?syn_keep:preserves nets?syn_preserve:preserves sequential components?syn_enum_encoding:determines encoding for enumerateddata types?syn_state_machine:extracts state ma

30、chine for a state register?syn_encoding:determines encoding for state machines?syn_probe:makes an internal net an output port to be used for probing?syn_direct_enable:extracts signal as clock enable to all flip flops it feedsTechnology Independent Attributes24Guidelines when Using Attributes in Veri

31、logGuidelines when Using Attributes in Verilog?All attributes are defined in comment statements and begin with keyword synthesis?Comment statements directly follow the object the attribute is being applied on?Before any“,”or“;”?Leave a space between the object name and the start of the comment?Synta

32、xobject/*synthesis attribute_name=*/;Technology Independent Attributes1325Guidelines when Using Attributes in VHDLGuidelines when Using Attributes in VHDL?All attributes are defined using the VHDL keyword attribute?The object on which the attribute is applied is defined before the value of the attri

33、bute is defined?The type of the attribute is defined?Define in the VHDL code before the value of the attribute is defined,or?Use predefined library package:library synplify;use synplify.attributes.all;?Syntax-if package synplify.attributes.all is used,this line is not requiredattribute attribute_nam

34、e:;-define value of attribute-object should be defined before the attribute on it isattribute attribute_name of object:object_type is;Technology Independent Attributes26syn_keepsyn_keep?Definition?Preserves a net throughout synthesis?Objects?Applies to wire or reg in Verilog,and signal in VHDL?Value

35、?Boolean?Syntax?Verilog Usageobject/*synthesis syn_keep=1*/;where object is a wire or reg?VHDL Usageattribute syn_keep of object:object_type is true;where object is a single or multi-bit signal.Technology Independent Attributes1427syn_keepsyn_keep?Common Usage?Prevent certain optimizations?Prevent s

36、haring of duplicate cells or registers?Preserve a net for simulation?Defining multi-cycle and false paths with-throughoption?Note?Applies only to nets and should not be applied toreg or signal that will become sequential devicesTechnology Independent Attributes28syn_keep with Multi-cycle Pathsyn_kee

37、p with Multi-cycle PathTechnology Independent AttributesUse syn_keep to specify only multout as a multi-cycle path.module mult_cyc_path(out,op,opa,opb,clk);input op,clk;input 7:0 opa,opb;output 15:0 out;wire 15:0 muxout;reg sel;reg 15:0 multout/*synthesis syn_keep=1*/;reg 15:0 addout;reg 7:0 add_mul

38、ta,add_multb;reg 15:0 out;always(posedge clk)beginsel=op;add_multa=opa;add_multb=opb;out=muxout;endalways(add_multa or add_multb)beginmultout=add_multa*add_multb;addout=add_multa+add_multb;endassign muxout15:0=sel?multout:addout;endmodule1529syn_keep Examplesyn_keep ExampleTechnology Independent Att

39、ributesmodule example2(out1,out2,clk,in1,in2);output out1,out2;input clk;input in1,in2;wire and_out;wire keep1 /*synthesis syn_keep=1*/;wire keep2 /*synthesis syn_keep=1*/;reg out1,out2;assign and_out=in1&in2;assign keep1=and_out;assign keep2=and_out;always(posedge clk)beginout1=keep1;out2=keep2;end

40、endmoduleUse syn_keep at the input of the registers to get registered outputs for out1 and out2Without syn_keep out1 and out2 optimize into one register.30syn_preservesyn_preserve?Definition?Prevents sequential optimization?Objects?Applies to reg or modules in Verilog,signal or architecture in VHDL?

41、Value?Boolean?Syntax?Verilog Usageobject/*synthesis syn_preserve=0|1*/;where object can be register definition signals or modules?VHDL Usageattribute syn_preserve of object:object_type is true|false;where object can be architectures or output ports and internal signals that hold the value of state r

42、egistersTechnology Independent Attributes1631syn_preserve Examplesyn_preserve ExampleTechnology Independent Attributesmodule syn_preserve(out1,out2,clk,in1,in2)/*synthesis syn_preserve=1*/;output out1,out2;input clk;input in1,in2;reg out1;reg out2;reg reg1;reg reg2;always(posedge clk)beginreg1=in1&i

43、n2;reg2=in1&in2;out1=!reg1;out2=!reg1®2;endendmoduleUse syn_preserve to keep reg2 and out2 register from getting optimizedWithout syn_preserve reg2 and out2registers are optimized with a warning32syn_enum_encodingsyn_enum_encoding?Definition?Defines how enumerated types are implemented?Objects?Ap

44、plies to enumerated types in VHDL?Value?String(“onehot”,“sequential”,“gray”or“default”)?Syntax?VHDL Usagetype type_name is();attribute syn_enum_encoding of type_name:type is;Technology Independent Attributes1733syn_enum_encoding Examplesyn_enum_encoding ExampleTechnology Independent Attributespackag

45、e testpkg istype mytype is(red,yellow,blue,green,white,violet,indigo,orange);attribute syn_enum_encoding:string;attribute syn_enum_encoding of mytype:type is sequential;end package testpkg;library IEEE;use IEEE.std_logic_1164.all;use work.testpkg.all;entity decoder isport(sel:in std_logic_vector(2 d

46、ownto 0);color:out mytype);end decoder;architecture rtl of decoder isWith syn_enum_encoding=“onehot”With syn_enum_encoding=“sequential”beginprocess(sel)begincase sel iswhen 000=color color color color color color color color=orange;end case;end process;end rtl;34syn_state_machinesyn_state_machine?De

47、finition?Enables/Disables state-machine inference?syn_state_machine overrides the check box for Symbolic FSM Compiler in the Synplify Pro UI?Objects?Applies to reg in Verilog,signal in VHDL that describes state registers?Value?Boolean?Syntax?Verilog Usageobject/*synthesis state_machine=0|1*/;where o

48、bject refers to state registers?VHDL Usageattribute syn_state_machine of object:object_typeis true|false;where object is a state registerTechnology Independent Attributes1835syn_state_machine Examplesyn_state_machine ExampleTechnology Independent Attributesmodule FSM1(clk,in1,rst,out1);input clk,rst

49、,in1;output 2:0 out1;reg 2:0 out1;reg 2:0 state/*synthesis syn_state_machine=1*/;reg 2:0 next_state;always(posedge clk or posedge rst)if(rst)state=s0;else state=next_state;/Combined Next State and Output Logicalways(state or in1)case(state)s0 :beginout1=3b000;if(in1)next_state=s1;else next_state=s0;

50、ends1 :beginout1=3b001;if(in1)next_state=s2;else next_state=s1;ends2 :beginout1=3b010;if(in1)next_state=s3;else next_state=s2;enddefault:beginout1=3bxxx;next_state=s0;endendcaseendmodulesyn_state_machine=1 causes a state machine to be inferredsyn_state_machine=036syn_encodingsyn_encoding?Definition?