VHDL数字电路课程实验报告.doc

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1、VHDL数字电路课程实验报告实验一 8分频器一、实验要求：分别用信号量和变量实现八分频器二、实验过程：1、代码：8分频器vhdlibrary ieee;use ieee.std_logic_1164.all;entity freq_divider isport(clk: in std_logic; out1, out2: buffer bit);end freq_divider;architecture example of freq_divider issignal count1: integer range 0 to 7;beginprocess(clk)variable count2:

2、integer range 0 to 7;beginif(clkevent and clk=1) thencount1=count1+1;count2:=count2+1;if(count1=3) thenout1=not out1;count1=0;end if;if(count2=4) thenout2=not out2;count2:=0;end if;end if;end process;end example;八分频器tbLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY fd_tb isEND fd_tb;architecture beh

3、avior of fd_tb iscomponent freq_dividerport(clk:IN STD_LOGIC; out1, out2: buffer bit);end component;signal clk:std_logic;signal out1,out2:bit;beginu1: freq_divider port map(clk,out1,out2);processbeginclk=0;wait for 50 ns;loopclk=not clk;wait for 25 ns;end loop;end process;end behavior;2、结果图：实验二 实现例8

4、.6一、 实验要求： 电路只有一个输入时钟信号，输出信号在适中的两个边沿都会发生变化二、 实验内容：1、 代码信号发生器vhdENTITY signal_gen IS PORT (clk: IN BIT; outp: OUT BIT);END signal_gen;ARCHITECTURE fsm OF signal_gen IS TYPE state IS (one, two, three); SIGNAL pr_state1, nx_state1: state; SIGNAL pr_state2, nx_state2: state; SIGNAL out1, out2: BIT;BEGIN

5、PROCESS(clk)BEGIN IF (clkEVENT AND clk = 1) THEN pr_state1 = nx_state1; END IF;END PROCESS;PROCESS (clk)BEGIN IF (clkEVENT AND clk = 0) THEN pr_state2 out1 = 0; nx_state1 out1 = 1; nx_state1 out1 = 1; nx_state1 out2 = 1; nx_state2 out2 = 0; nx_state2 out2 = 1; nx_state2 = one; END CASE;END PROCESS;o

6、utp = out1 AND out2;END fsm;信号发生器tbentity tb_fsm isend tb_fsm;architecture behavior of tb_fsm iscomponent signal_gen isport( clk: in bit; outp: out bit);end component;signal clk,outp:bit;beginu1: signal_gen port map(clk,outp);processbeginclk=0;wait for 20 ns;loopclk=not clk;wait for 10 ns;end loop;e

7、nd process;end behavior;2、 结果图实验三 常数比较器一、 实验要求 常数比较器，用于比较的变量位宽应大于等于常数二、 实验内容1、 代码常数比较器vhdLIBRARY ieee;USE ieee.std_logic_1164.all;entity compare isport(b: in integer range 0 to 15; x1,x2,x3: out std_logic);end compare;architecture compare of compare isconstant a: integer:=10;beginx1b else 0;x2=1 whe

8、n a=b else 0;x3=1 when ab else 0;end compare;常数比较器tbLIBRARY ieee;USE ieee.std_logic_1164.all;entity tb_compare isend tb_compare;architecture behavior of tb_compare iscomponent compareport(b: in integer range 0 to 15; x1,x2,x3: out std_logic);end component;signal b: integer;signal x1,x2,x3: std_logic

9、;beginu1: compare port map(b, x1,x2,x3);processbeginb=5; wait for 10 ns;b=8; wait for 10 ns;b=10; wait for 10 ns;b=13; wait for 10 ns;b=10; wait for 10 ns;b=3; wait for 10 ns;end process;end behavior;2、 结果图实验四 序列检测器一、 实验要求 序列检测1001 弱检测到，输出1，否则输出0二、 实验内容1、 状态图Zeroq=0fourq=1twoq=0oneq=0threeq=0d=0d=1d

10、=1d=1d=1d=1d=0d=0d=0rstd=02、 代码序列检测器vhdlibrary ieee;use ieee.std_logic_1164.all;entity string_detector isport(datain,clk: in bit; q: out bit);end string_detector;architecture sd of string_detector istype state is (zero, one, two, three, four);signal pr_state, nx_state: state;beginprocess(clk)beginif

11、(clkevent and clk=1) thenpr_stateq=0;if(datain=1) then nx_state=one;else nx_stateq=0;if(datain=0) then nx_state=two;else nx_stateq=0;if(datain=0) then nx_state=three;else nx_stateq=0;if(datain=1) then nx_state=four;else nx_stateq=1;nx_state=zero;end case;end process;end sd;序列检测器tb-library ieee;use i

12、eee.std_logic_1164.all;-entity testBench isend testBench;-architecture test of testBench is component string_detector is port(datain,clk: in bit; q: out bit); end component; signal datain,clk:bit; signal q:bit;begin SD: string_detector port map(datain,clk,q); process begin for i in 0 to 100 loop clk

13、=0; wait for 10 ns; clk=1; wait for 10 ns; end loop; end process; process begin din=1; wait for 20ns; din=0; wait for 20ns; din=0; wait for 20ns; din=0; wait for 20ns; din=1; wait for 20ns; din=0; wait for 20ns; din=0; wait for 20ns; din=1; wait for 20ns; din=0; wait for 20ns; din=1; wait for 20ns; din=0; wait for 20ns; end process;end test;3、 结果图