《主板基础知识》PPT课件.ppt

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1、M/B Design BasicsDWHD-PCA-EE:TuneRoadmap1M/B Block Diagrams2M/B basic components R/L/C3M/B basic components Chipset4M/B basic components Super I/O5M/B basic components CPU6PCIE Introduction78B/10B CodingM/B Block DiagramsFSBDMIDDR2 channel AVGA/DVI/HDMIPCIE X16USB2.0(12 Ports)SATAII interfaceDDR2 ch

2、annel BPCI interfaceCom PortPrinter PortPS/2 PortFloppy PortHD AudioNetwork PHY I/FPCIE X1 interfaceM/B Block Diagrams Actual M/BM/B basic components RResistor specificationPower Rating:(rated power 70 degree)p RC0402 1/16 Wp RC0603 1/10 Wp RC0805 1/8 Wp RC1206 1/4 WRated Voltage:the DC or AC(rms)co

3、ntinuous working voltage corresponding tothe rated power is determined by the following formula.Electrical characteristicpoperating temp rangepmaximum working voltagepMaximum overload voltagepDielectric withstanding voltagepResistance rangepTemp coefficientResistor application on mother board1)Jumpe

4、r for reserved design or debug,often 0 resistor;2)Pull up or pull down to some logic level3)Impedance match for clock and high speed signal4)For power,used as damping resistor,power bleed offM/B basic components CSMDCapacitor specificationSize:p RC0402p RC0603 p RC0805p RC1206Rated Voltage:10V,16V,2

5、5V,50VElectrical features:p operating temp rangep Capacitance tolerancep operating temperaturep Load lifep case sizecapacitor application on mother board1)Power decoupling to stabilize a signal or power rail2)EMI signal sink,100pF,150pF3)RC delay,such as 100nF,1uF4)High speed signal coupling,such as

6、 100nFTolerance:p NPOp X5Rp X7Rp Y5Vp M5UM/B basic components CPTHCapacitor specificationParameter:p Capacitancep ESR,p Dissipation Factorp Impedancep Leakage currentElectrical characteristicpoperating temp rangepmaximum working voltagepMaximum overload voltagepDielectric withstanding voltagepResist

7、ance rangepTemp coefficientE-Capacitor application on mother board1)Power decoupling,to stabilize power rail2)Audio Signal coupling3)Low ESR cap,for ripple current filterTolerance:p Al ECAPp OS-CON FP CAPM/B basic components LSMDCapacitor specificationType:p Chip inductor Signal Thin Film Chip Induc

8、tor Multilayer Chip Inductor Wire Wound Chip Inductorp Ferrite bead-EMI Differential mode Common modep Power InductorElectrical characteristicpoperating temp rangepmaximum working voltagepMaximum overload voltagepDielectric withstanding voltagepResistance rangepTemp coefficientChip inductor applicat

9、ion on mother boardpDepress the noise into power pSignal process,impedance matchas a signal filter such as power and VGA signalas EMI filter.USB signal,common mode noise depresspFor power processTolerance:p 5%,10%p 20%,25%M/B basic components LDIPChoke specificationProcess:p IRON Coilp PMCParameter:

10、p L:inductance valuep RDC:internal DC resistorp IDC:rating currentp Q:p Test Frequencyp working temperaturep resonant frequencyElectrical characteristicpoperating temp rangepmaximum working voltagepMaximum overload voltagepDielectric withstanding voltagepResistance rangepTemp coefficientchoke applic

11、ation on mother board1)Power process,DC-DC power output choke2)EMI filter,DC-DC power input chokeM/B basic components chipset GMCHHost Interface:p FSB GTL ClockGraphics I/Fp VGAp DVI/HDMIp PCIE X16 DMI Interfacep DMI LINKMemory Interfacep DDRIIp DDR IIIp Maximum 8GBp Dual Channel,4-DIMMNB function o

12、n mother board1)Host interface to CPU,and make a bridge between the ICH,Memory,Graphics and CPU.2)Integrated core:PCI/PCIE bridge,Memory controller,AGP,PCIE/PCI to Host bridge3)NB capability:Graphics process:to support the Direct X9.0,10.0 rendering technology Display/Media Content:HDMI/DVI/Display

13、Port,HD-DVD,Blue-Ray Memory speed:to match with memory type or speed FSB speed:to match with CPU FSB M/B basic components chipset ICHHost Interface:p DMI to GMCHp pointto-point linkStoragep SATAII 3Gb/sp RAIDNetwork Interfacep LCI/GLCIp Ethernet PHYUSB2.0 Interfacep 12 Portsp 6 UHCIp 2 EHCIp USB leg

14、acy supportExpand SlotPCI Rev2.3,3 SlotsPCIE X1,6 SlotsSB function on mother board1)Host interface to NB,and make a bridge between the SIO,PCI,PCIE,and NB.2)Integrated core:PCI/PCIE bridge,PIDE/SATA controller,Audio Link,Network PHY,legacy core:RTC,interrupt controller,SM bus controller,APIC control

15、ler3)NB capability:Storage:to support the Direct X9.0,10.0 rendering technology Expandability:support PCI,PCIE numbers Network:Ethernet PHY Audio Link:AC97,HDAAudio Interfacep HAD LinkM/B basic components Super I/OLPC Interface:p connect to SBp multi-drop,similar to PCIStoragep FloppyCOM Portp Modem

16、p serial port Keyboardp serial communicationPrinter PortLegacy printer portPS/2p Keyboardp MouseSIO function on mother board1)To provide the communication path for legacy device to ICH2)Integrated legacy core:UART,Floppy controller,Printer controller,PS/2 controller,M/B basic components CPUDesktop P

17、rocessorPerformance/Features:cores numbers on-chip Shared Cache Size Simultaneous Multi-Threading capability(SMT)FSB/QPI New instructionsPower:65W,95W,130W FMBSocket:p mPGA478p LGA775 socketp LGA1336 socketProcess Technology:p 130 nm,Prescottp 90 nm,p 65 nm,Conroep 45 nm,wolf daleM/B basic component

18、s CPU exampleDesktop Bloomfield ProcessorPerformance/Features:4 cores 8M on-chip Shared Cache Simultaneous Multi-Threading capability(SMT)Intel Quick Path Interconnect(QPI)Integrated Memory Controller (IMC)New instructionsPower:130W FMBSchedule Q108 First samples Q408 LaunchHEDT Socket:New LGA1336 S

19、ocketProcessor Technology:45nm CPUM/B basic components CPU TrendDesktop Processor new technologyFast Radix-16 DividerFaster OS Primitive SupportEnhanced Intel Virtualization Technology Larger Caches:up to 12 MB24 Way Set AssociativelyIntel Wide Dynamic ExecutionIntel Advanced Smart Cache Split Load

20、Cache EnhancementImproved Store ForwardingHigher bus speeds Intel SSE4 instructionsSuper Shuffle EngineDeep Power Down TechnologyEnhanced Intel Dynamic Acceleration TechIntel Smart Memory AccessIntel Advanced Digital Media BoostIntel Intelligent Power CapabilityIntel Core Micro architectureNew with

21、the Penryn FamilyPCIE Introduction-Key Attributesn Scalable Width,Frequencyn Higher Bandwidthn Consolidate the I/On Unify proliferated segmentsn Works in existing PCI EnvironmentHighPerformanceI/OSimplificationn Layered Architecture=longevityn Reliability,Availability,Serviceabilityn Advanced Power

22、Managementn Virtual Channelsn Quality of Service/Isochronesn New Form Factors/Innovative Designsn Hot Plug/Hot SwapAdvancedArchitectureNext Gen 3D/MultimediaEase of UsePCIE Introduction-ArchitecturePhysical LayerLink LayerTransaction LayerLayer 4+MarketSegmentOptimizationsL1/L2CommonalityPCIE Introd

23、uction-Transaction Layerp Initialization and configurationp Packet generation and process servicep Flow control servicep Ordering rules p Split Transaction Posted and non-posted requests non-posted request require completionsp Transaction Types Memory,I/O,Configuration,MessageHeaderDatePCIE Introduc

24、tion-Data Link Layerp Link Management initialization and power managementp Data integrity Data protection,error checking,and retry services TLP sequence number Data Protection CodeHeaderDateSeq.#CRCPCIE Introduction-Physical Layerp Initialization and configurationp Packet generation and process serv

25、icep Flow control servicep Ordering rulesHeaderDateSeq.#CRCFramingFramingPCIE Introduction-Definitions8B/10B Coding-Part 1 History/application The code was described in 1983 by Al Widmer and Peter Franaszek in the IBM Journal of Research and Development.IBM was issued a patent for the scheme the fol

26、lowing year.IBMs patent notwithstanding,the method,implementation and goals are very similar to Group Code Recording(GCR)used on floppy disks in some computers during late 1970s/early 80sHistoryApplicationPCI Express IEEE 1394b Serial ATA SAS Fiber Channel SSA Hyper TransportInfiniBand XAUI Serial R

27、apidIO DVI(Transition Minimized Differential Signaling)DVB Asynchronous Serial Interface(ASI)Gigabit Ethernet(except for the twisted pair based 1000Base-T)8B/10B Coding-Part 2 How it worksHow it worksAs the scheme name suggests,8 bits of data are transmitted as a 10-bit entity called a symbol,or cha

28、racter.The low 5 bits of data are encoded into a 6-bit group and the top 3 bits are encoded into a 4-bit group.These code groups are concatenated together to form the 10-bit symbol that is transmitted on the wire.Because 8b/10b encoding uses 10-bit symbols to encode 8-bit words,some of the possible

29、1024 codes can be excluded to grant a run-length limit of 5 consecutive equal bits and grant that the difference of the count of 0s and 1s is no more than 2.Some of the 256 possible 8-bit words can be encoded in two different ways.Using these alternative encodings,the scheme is able to affect long-t

30、erm DC-balance in the serial data stream.The encoding is normally done entirely in hardware.Upper layers of the software stack should be unaware that this encoding is being used.8B/10B Coding-Part 2 Code TableinputRD=-1RD=+1inputRd=-1Rd=+1HGFfghjHGFfghjD.x.000011010100K.x.000010110100D.x.10011001K.x

31、.1200101101001D.x.20100101K.x.2200110100101D.x.301111000011K.x.301111000011D.x.410011010010K.x.410011010010D.x.51011010K.x.5200101011010D.x.61100110K.x.6200110010110D.x.P7111111100001D.x.A7111101111000K.x.A72111011110003B/4BNote 1:For D.x.7,the Primary(D.x.P7)or Alternate(D.x.A7)encoding must be sel

32、ected in order to avoid a run of five consecutive 0s or 1s when combined with the preceding 5b/6b code.Sequences of five identical bits are used in comma codes for synchronization issues.D.x.A7 is only used for x=17,x=18 and x=20 when RD=-1 and for x=11,x=13 and x=14 when RD=+1.With x=23,x=27,x=29 a

33、nd x=30,the same code forms the control codes K.x.7.Any other x.A7 code cant be used as it would result in chances for misaligned comma sequences.Note 2:The alternate encoding for the K.x.y codes with disparity 0 allow for K.28.1,K.28.5 and K.28.7 to be comma codes that contain a bit sequence that c

34、ant be found elsewhere in the data stream8B/10B Coding-Part 2 Code Table5B/6BinputRD=-1RD=+1HGF EDCBAAbcdei fghjAbcdei fghjK.28.0000 11100001111 0100110000 1011K.28.1001 11100001111 1001110000 0110K.28.2010 11100001111 0101110000 1010K.28.3011 11100001111 0011110000 1100K.28.4100 11100001111 0010110

35、000 1101K.28.5101 11100001111 1010110000 0101K.28.6110 11100001111 0110110000 1001K.28.7111 11100001111 1000110000 0111K.23.7111 10111111010 1000000101 0111K.27.7111 11011110110 1000001001 0111K.29.7111 11101101110 1000010001 0111K.30.7111 11110011110 1000100001 01118B/10B Coding-Part 2 Code Tablein

36、putRD=-1RD=+1HGF EDCBAAbcdei fghjAbcdei fghjK.28.0000 11100001111 0100110000 1011K.28.1001 11100001111 1001110000 0110K.28.2010 11100001111 0101110000 1010K.28.3011 11100001111 0011110000 1100K.28.4100 11100001111 0010110000 1101K.28.5101 11100001111 1010110000 0101K.28.6110 11100001111 0110110000 1001K.28.7111 11100001111 1000110000 0111K.23.7111 10111111010 1000000101 0111K.27.7111 11011110110 1000001001 0111K.29.7111 11101101110 1000010001 0111K.30.7111 11110011110 1000100001 0111Control symbols