最新大规模数字集成电路设计第二章VHDL语言程序的基本结构教学课件.ppt

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1、大规模数字集成电路设计第大规模数字集成电路设计第二章二章VHDLVHDL语言程序的基本结语言程序的基本结构构本章要点本章要点VHDL程序的宏观结构；程序的宏观结构；实体的基本格式及其在实体的基本格式及其在VHDL硬件设计硬件设计中的应用中的应用构造体的基本格式及其在构造体的基本格式及其在VHDL硬件设硬件设计中的基本功能计中的基本功能库的实用意义及使用方法。库的实用意义及使用方法。2.3 2.3 构造体构造体 构造体的结构构造体的结构ARCHITECTURE 构造体名构造体名 OF 实体名实体名 IS【定义语句】【定义语句】内部信号、常数、数据类型等的定义内部信号、常数、数据类型等的定义；BE

2、GIN【并行处理语句】【并行处理语句】；END 构造体名构造体名；2.3 2.3 构造体构造体 1）构造体的命名）构造体的命名 2）定义语句）定义语句 3）并行处理语句）并行处理语句2.3 2.3 构造体构造体 一个完整的构造体由两个基本层次组成：一个完整的构造体由两个基本层次组成：2)描述实体逻辑行为的，以各种不同的描描述实体逻辑行为的，以各种不同的描述风格表示的功能描述语句。述风格表示的功能描述语句。1）对数据类型，常数，信号，子程序和元对数据类型，常数，信号，子程序和元件等元素的说明部分。件等元素的说明部分。【例【例1 1】二选一选择器二选一选择器ANDNOTANDORD1SELD0Qt

3、mp1tmp2MUX2ID0Entity mux2id0 isPort(d0,d1,sel:in bit;q:out bit);End mux2id0;Architecture struc of mux isBeginprocess(d0,d1,sel)variable tmp1,tmp2,tmp3:bit;begintmp1:=d0 AND sel;tmp2:=d1 AND(NOT sel);q=tmp1 OR tmp2;end process;End struc;【例【例1】二选一选择器二选一选择器【例【例 1-2】二选一选择器的构造体说明二选一选择器的构造体说明(续续)ARCHITECT

4、URE connect OF mux IS-构造体定义构造体定义BEGIN-构造体开始标记构造体开始标记 PROCESS(d0,d1,sel)-进程进程 VARIABLE tmp1,tmp2,tmp3:BIT;-变量的声明变量的声明 BEGIN-进程开始标记进程开始标记 tmp1:=d0 AND sel;-变量赋值语句变量赋值语句 tmp2:=d1 AND(NOT sel);-变量赋值语句变量赋值语句 q=tmp1 OR tmp2;-信号赋值语句信号赋值语句 END PROCESS;-进程结束进程结束END connect;-构造体结束构造体结束【例【例 1-2】二选一选择器的构造体说明二选一

5、选择器的构造体说明(续续)ARCHITECTURE connect OF mux IS-构造体定义构造体定义BEGIN-构造体开始标记构造体开始标记 PROCESS(d0,d1,sel)-进程进程1。END PROCESS;-进程进程1结束结束 PROCESS(d0,d1,sel)-进程进程2。END PROCESS;-进程进程2结束结束 。-其它并行语句结构其它并行语句结构 END connect;-构造体结束构造体结束Used to make associations within models Associate a Entity and Architecture Associate a

6、 component to an Entity-ArchitectureWidely used in Simulation environments Provides a flexible and fast path to design alternatives Limited or no support in Synthesis environmentsCONFIGURATION OF ISFOR END FOR;END;(1076-1987 version)END CONFIGURATION;(1076-1993 version)2.4 2.4 配置配置（Configuration）Put

7、ting it all together Packages are a convenient way of storing and using information throughout an entire model.Packages consist of:Package Declaration(Required)Type declarationsSubprograms declarations Package Body(Optional)Subprogram definitions VHDL has two built-in Packages Standard TEXTIO2.4 2.4

8、 包集合（包集合（Package）2.5 库库Contains a package or a collection of packages.Resource Libraries Standard Package IEEE developed packages Altera Component packages Any library of design units that are referenced in a design.Working Library Library into which the unit is being compiled.必须放在VHDL程序最前面;在VHDL程序中

9、，可以有多个库，库和库之间相互独立;All packages must be compiled Implicit Libraries Work STD Note:Items in these packages do not need to be referenced,they are implied.LIBRARY Clause Defines the library name that can be referenced.Is a symbolic name to path/directory.Defined by the Compiler Tool.USE Clause Specifies

10、 the package and object in the library that you have specified in the Library clause.2.5 库库LIBRARY STDn Contains the following packages:standard(Types:Bit,Boolean,Integer,Real,and Time.All operator functions to support types)textio(File operations)n An implicit library(built-in)Does not need to be r

11、eferenced in VHDL designTypes defined in Standard Packagen Type BIT 2 logic value system(0,1)signal a_temp:bit;BIT_VECTOR array of bitssignal temp:bit_vector(3 downto 0);signal temp:bit_vector(0 to 3);n Type BOOLEAN(false,true)n Integer Positive and negative values in decimalsignal int_tmp:integer;-

12、32 bit numbersignal int_tmp1:integer range 0 to 255;-8 bit numberNote:Standard package has other types2.4.1 库的种类库的种类1）IEEE库std_logic_1164(std_logic types&related functions)std_logic_arith(arithmetic functions)std_logic_signed(signed arithmetic functions)std_logic_unsigned(unsigned arithmetic functio

13、ns)2）STD库 standard(Types:Bit,Boolean,Integer,Real,and Time.All operator functions to support types)textio(File operations)LIBRARY IEEEContains the following packages:std_logic_1164(std_logic types&related functions)std_logic_arith(arithmetic functions)std_logic_signed(signed arithmetic functions)std

14、_logic_unsigned(unsigned arithmetic functions)Types defined in std_logic_1164 Packagen Type STD_LOGIC 9 logic value system(U,X,0,1,Z,W,L,H,-)W,L,H”weak values(Not supported by Synthesis)X-used for unknown Z-(not z)used for tri-state-Dont Care Resolved type:supports,signals with multiple drives.n Typ

15、e STD_ULOGIC Same 9 value system as STD_LOGIC Unresolved type:Does not support multiple signal drives.Error will occur.2.4.1 库的使用库的使用1）库的声明LIBRARY library_name;USE library_name.package_name.ITEM.name;2）库的使用范围从一个实体说明开始到它所属的构造体、配置为止。【例2】二选一选择器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux ISGENER

16、IC (m:TIME:=1ns);PORT(d0,d1:IN STD_LOGIC_VECTOR(7 DOWNTO 0);sel:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END mux;Putting it all togetherVHDL描述的总体结构描述的总体结构作 业 请请写写出出带带同同步步清清零零端端clr的的D触触发发器器的的实体部分。实体部分。IN输入输入OUT输出输出INOUT双向双向BUFFER输出，构造体内部可再使用输出，构造体内部可再使用LINKAGE不指定方向，无论哪个方向都可不指定方向，无论哪个方向都可连接连接标准数据类型标准数据类型Package Example结束语结束语谢谢大家聆听！谢谢大家聆听！41