多核高速并行数字信处理板设计方案及应用v.pdf

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1、1/7 多核高速并行数字信号处理板设计及应用摘要随着 DSP芯片生产制造技术的日益发展，基于多核的高性能DSP在通信与信息系统、信号与信息处理、自动控制、雷达、军事、航空航天、医疗、家用电器等许多领域获得越来越多的应用。本文将介绍基于4片ADSP-TS201的高速并行数字信号处理板的软硬件设计及在某雷达相参处理设备中的应用。关键词 高速 DSP；TS201；并行计算；相参处理Design and Application of Multi-core High-speed Parallel Digital Signal Processing Board AbstractWith growing m

2、anufacturing technology of DSP chips,high-performance multi-CPU DSP gets more and more applicationsin communications and information systems,signal and information processing,automatic control,radar,military,aerospace,medical,household appliances and many other areas.This paper describes the hardwar

3、e and software designof a high-performance DSP board based on 4 ADSP-TS201,and then shows an application example in a radar phase processing equipment.Key WordsHigh-speed DSP,TS201,parallel compute,phase processing 1 引言随着实时信号处理的发展，数据处理速度大大提高，同时运算量大，数据吞吐量急剧上升，对数据处理的要求也不断提高。随着大规模集成电路技术的发展，作为数字信号处理的核心数

4、字信号处理器(DSP得到了快速的发展和应用。ADSP-TS201DSP 是美国模拟器件公司 操作；采用 LVDS技术和 DDR 方式传输数据，单向最大速率为500 MB/s，数据吞吐量为4 GB/s；4条128位数据总线可与*MB 的 RAM 相连，其 34位地址总线可提供4GB的寻址空间；有4个链路口，每个链路口可提供1.2 GB s的传输速率，并可同时进行DMA 传输；可通过共享总线提供无缝连接以用于片内集成总线的仲裁控制；片上 SDRAM 控制器和片上 DMA 控制器可提供 14条DMA 通道。2.2 系统结构设计该DSP板主要由四片 TS201芯片，一片 Altera EP2S90系列

5、 FPGA芯片组成。同时使用了一些RAM、FLASH 和SDRAM 器件来存储系统中的数据和程序。系统与外部进行通信的接口主要采用CPCI总线接口。本设计采用DSP结合FPGA 的方式。这种方式最大的优点就是结构灵活，有较强的通用性，适合模块化设计，并能够提高效率，同时，其开发周期较短，系统容易维护和扩展，所以，这种结构目前比较流行。该系统的结构框图如图1所示。多DSP设计通常有共享总线方式和链路口耦合方式两种结构。共享总线结构的优点是可以提供全局地址空间，把多DSP的地址空间映射到主机的内存空间进行统一访问。任一DSP也可通过总线读写其它处理器内存，操作方便。当多DSP间数据交换频繁时，总线

6、竞争往往造成数据通信的总线瓶颈，则采用链路口耦合方式，各DSP总线独立，拥有完全独立的内存空间，各DSP程序设计可完全独立，减小了程序调试的难度。各DSP之间仅通过链路口无缝连接，片间连线少，降低了PCB布线难度和层数，节约了制板成本。此外，数文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10

7、U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1

8、B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2

9、C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10

10、U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1

11、B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2

12、C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10

13、U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U13/7 据传输采用链路口的DMA 方式并不占用DSP内核的运算时间，可以提高处理板的实时性能。因而采用将 4片ADSP-TS201通过链路口两两互连，形成松耦合的多DSP结构，各 DSP通过链路口可在任意两个DSP之间进行最高达480

14、MB s的数据传输。图 1 系统结构框图该DSP板内核时钟 500MHz，单板提供每秒120亿次浮点处理能力。TS201之间总线互连，构成一簇，簇内DSP之间使用链路口互连，TS201之间通信速率为480MB/s。整板具有512MB 外部缓冲数据存储器SDRAM，DMA 方式读写 SDRAM 峰值速率可达320MB/s。DSP簇对外提供 4个链路口用于板间互连，总带宽400MB/s，可实现多板并行处理扩展。并可通过CPCI接口实现与数据采集板等其他设备进行通信，组合成完整的高速数据采集、并行处理系统。2.3 系统软件设计本系统采用 Visual DSP+开发平台进行软件设计。Visual DS

15、P+是一种使用方便的可视化集成调试开发软件平台，它支持ADI 公司浮点系列处理器的各种产品(如SHARC 系列，BLACKfin 系列和 TigerSHARC 系列。它可以通过可视化的图形窗口方式与用户进行信息交换，也可以在窗口中进行高效的工程管理，并轻松地在编辑、编译和调试之间相互切换，以实现高效率的程序开发。文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ1

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21、K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ1

22、0C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U14/7 基于多个 TS201的DSP板软件设计主要包括以下几个方面：1多处理器系统构建当系统中存在多个处理器，且用户想一起控制调试这些处理器时，必须要为协调功能进行额

23、外的编程，以便调试和构建多处理器系统。如建立统一的存储空间映射、多处理器间通信及数据传输方式等。2存储空间系统存储空间包括TS201内存空间和 SDRAM 外部存储器。软件设计过程中可通过总线直接读写的方式访问内存和SDRAM，或通过 DMA 方式实现内存和SDRAM 之间的后台数据传输。3多处理器数据传输多处理器系统往往需要进行海量数据流的交互，以提高系统的工作效率。通常通过DSP之间的总线直接读写、链路口DMA 等方式进行数据传输。也可以通过统一访问SDRAM 实现间接数据传输。4矢量中断(VIRPT 矢量中断用于FPGA和 DSP之间，或者 DSP和 DSP之间的通信。通过把中断子程序的

24、地址写入 VIRPT 寄存器，当服务中断时，高优先级中断将使DSP转到子程序地址，以服务该子程序。本DSP板多处理器之间、处理器与FPGA之间、以及 FPGA对外部设备均留有丰富的接口，通过灵活的软件设计，可满足多种高性能信号处理领域的应用。3 典型应用分析3.1 雷达信号相参处理应用3.1.1 需求分析近年来我国的雷达技术已获得了飞速的进步，雷达的制造水平已和西方发达国家相近。但是目前我军仍有大量非相参雷达在役使用及库存。特别是一些老式的M波雷达，虽然存在着探测能力低，杂波区干扰大等缺点，与新型全相参雷达相比有较大的差距，但是对隐身目标还保持着一定的探测能力。利用器件工业的最新发展成就，采用

25、接收端相参的办法对非相参雷达进行相参改造，具有操作使用简单方便、工作稳定可靠、效果好、通用性强、投资小等优点。为解决非相参雷达的杂波对消和对弱小信号的检测问题提供了稳定可靠的解决途径。数据处理流程如文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3

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28、9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3

29、I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:C

30、J10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K

31、9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3

32、I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U15/7 图 2 所示。由于算法的复杂度增加，加上M波脉冲雷达的频率特性和波形设计特点，通常需要在指定脉冲周期内实时完成对大量数字信号的实时处理，因此需要高速DSP板进行并行处理以满足探测精度和实时性的要求。多点复数相关数据率4M/S数据 1/8抽取数据率500K/SMTD/MTI所

33、有距离元检波所有距离元检波恒虚警处理恒虚警处理远处视频信号非相参积累近处杂波区MTD恒虚警处理根据噪底实现幅度归一化数据率500K/S同一距离元选大输出视频数据率500K/S数据率500K/S数据率500K/S图 2 数据处理流程3.1.2 信号处理流程设计由于处理的数据量大、实时性要求高以及算法复杂度高，本实例中充分利用TS201适合多核设计的特性进行并行数字信号处理设计。四片TS201未经过处理原始信号：SNR=5dB (b经过相参积累的信号：SNR=20dB 图 3 非相参与相参处理结果对比可见，相参处理能够实现有效的相参积累，提高微弱目标的信噪比，从而有效提高雷达对微弱目标的发现能力。

34、而通过时间重叠、资源重复等多种并行处理方式，大大的提高了系统加速比，实现了实时、高速的数字信号处理。3.2 扩展应用由于该 DSP板的高速处理能力和软件设计灵活性，也可充分满足如下领域中的应用：语音信号处理：语音增强、语音识别、语音合成、语音编码、文字转换等；图形/图像处理：三维动画、图像鉴别/增强/压缩/传输，模式识别、电子地图等；特殊应用数字信号处理：振动和噪声分析与处理、声纳和雷达信号处理、地震信号分析与处理等。4 结语本文介绍了一款基于ADSP-TS201的高速数字信号处理板的软硬件设计及在某雷达相参处理设备中的应用，由于该信文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2

35、 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8

36、S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1

37、文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2

38、 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8

39、S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1

40、文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2

41、 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8

42、S5 HW3I5K10E1B2 ZG10K9I10L10U17/7 号处理板的灵活性和可扩展性，同时也可以满足多个领域的应用需求。参考文献1 张虎堂.数字信号处理器(DSP的发展趋势与应用研究J.SILICON VALLEY,2018,(23 2 彭启琮,李玉柏,管庆.DSP技术的发展与应用M.北京:高等教育出版社,2007.作者信息郭晨冰，男，中国船舶重工集团公司第七一三研究所，郑州，硕士研究生，机械电子工程，450015 文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10

43、L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K1

44、0E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C

45、9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10

46、L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K1

47、0E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C

48、9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1文档编码:CJ10C9Y2C8S5 HW3I5K10E1B2 ZG10K9I10L10U1