2022年QuartusII使用教程-完整实例 .pdf
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1、Quartus 入门教程(一个 Verilog 程序的编译和功能仿真)Quartus 是 Altera 公司推出的专业EDA 工具,支持原理图输入、硬件描述语言的输入等多种输入方式。硬件描述语言的输入方式是利用类似高级程序的设计方法来设计出数字系统。接下来我们对这种智能的EDA 工具进行初步的学习。使大家以后的数字系统设计更加容易上手。第一步:打开软件快捷工具栏:提供设置(setting),编译(compile)等快捷方式,方便用户使用,用户也可以在菜单栏的下拉菜单找到相应的选项。菜单栏:软件所有功能的控制选项都可以在其下拉菜单中找到。信息栏:编译或者综合整个过程的详细信息显示窗口,包括编译通
2、过信息和报错信息。快捷工具栏信息栏菜单栏工作区资源管理窗口任务管理窗口第二步:新建工程(filenew Project Wizard)1 工程名称:2 添加已有文件(没有已有文件的直接跳过next)所建工程的保存路径工程名称顶层模块名(芯片级设计为实体名),要求与工程名称相同如 果有已经存在的文件就在该过程中添加,软 件将直接将用户所添 加的文件添加到工程中。文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2
3、K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I
4、6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2
5、G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8
6、R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX
7、8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9
8、Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3
9、E8R2K6D1文档编码:CX8I6M7X9K6 HR9Y2G10P6P1 ZJ3E8R2K6D13 选择芯片型号(我们选择MAX3000A 系列下的EPM3256AQC208-10芯片)(注:如果不下载到开发板上进行测试,这一步可以不用设置)4 选择仿真,综合工具(第一次实验全部利用quartus 做,三项都选None,然后 next)所选的芯片的系列型号快速搜索所需的芯片选择芯片文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6
10、G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K
11、3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4
12、Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8
13、V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H
14、6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9
15、Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7
16、H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W15 工程建立完成(点finish)选择第三方综合工具,如果使用 Quartus 内部综合工具则选择 none 选择第三方仿真工具,如果使用 Quartus 内部仿真工具则选择 none 选择时序分析仪工程建立完成,该窗口显示所建立工程所有的芯片,其他第三方EDA 工具选择情况,以及模块名等等信息。文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9
17、Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7
18、H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P
19、8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:C
20、B9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 H
21、X7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU
22、6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码
23、:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1第三步:添加文件(filenew VHDL file),新建完成之后要先保存。第四步:编写程序以实现一个与门和或门为例,Verilog 描述源文件如下:module test(a,b,out1,out2);input a,b;Output out1,out2;assign out1=a&b;assign out2=a|b;endmodule 然后保存源文件;第五步:检查语法(点击工具栏的这个按钮(start Analysis&synthes
24、is)我们选择Verilog HDL File设计文件格式既选择Verilog文本输入形式文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q
25、4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H8V6G5P1 ZU6P8H6K3W1文档编码:CB9Q4Z5B7T10 HX7H
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