高级操作系统高级操作系统 (34).pdf
《高级操作系统高级操作系统 (34).pdf》由会员分享,可在线阅读,更多相关《高级操作系统高级操作系统 (34).pdf(55页珍藏版)》请在淘文阁 - 分享文档赚钱的网站上搜索。
1、第 12 讲:Scalable Synchronization on Shared-MemoryMultiprocessors-IIMultiprocessor Memory Model&Multiprocessor ProgrammingRecapCache Coherent in Multi-processorMSI 一致性协议MESI 一致性协议ref:Some info are fromPaul McKenney(IBM)Tom Hart(University of Toronto),Frans Kaashoek(MIT),Daniel J.Sorin”A Primer on Memo
2、ry Consistency and Cache Coherence”,Fabian Giesen”Cache coherency primer”,Mingyu Gao(Tsinghua),Yubin Xia(SJTU)”The C/C+Memory Model:Overview and Formalization”,Mark Batty,etc.”C+11 Memory ConsistencyModel”,Sebastian Gerstenberg;”HOW UBISOFT MONTREAL DEVELOPS GAMES FOR MULTICORE Before&After C+11”,Je
3、ff Preshing;etc.RecapMemory Consistency in Multi-processorSequential ConsistencyTotal Store Order ConsistencyAcquire/Release ConsistencyRelaxed/Weak Consistency.Multiprocessor Programming陈渝(清华大学)第 12 讲2020 年 5 月 9 日4/55.Ways to Achieve Synchronizes-WithC+11/17/20,Go,RUST,Java,陈渝(清华大学)第 12 讲2020 年 5
4、月 9 日5/55.Real Hardware/CompilerReal hardware doesnt run the code that you wrote.Real compiler doesnt produce the code that you wrote.陈渝(清华大学)第 12 讲2020 年 5 月 9 日6/55.Real Hardware/CompilerReal hardware doesnt run the code that you wrote.Real compiler doesnt produce the code that you wrote.http:/ 12
5、 讲2020 年 5 月 9 日7/55.Real Hardware/CompilerReal hardware doesnt run the code that you wrote.Real compiler doesnt produce the code that you wrote.根据英特尔的规范:在本示例的末尾,r1 和 r2 都等于 0 是合法的陈渝(清华大学)第 12 讲2020 年 5 月 9 日8/55.Real Hardware/CompilerReal hardware doesnt run the code that you wrote.Real compiler do
6、esnt produce the code that you wrote.陈渝(清华大学)第 12 讲2020 年 5 月 9 日9/55.Real Hardware/CompilerReal hardware doesnt run the code that you wrote.Real compiler doesnt produce the code that you wrote.https:/ 12 讲2020 年 5 月 9 日10/55.Real Hardware/CompilerReal hardware doesnt run the code that you wrote.Rea
7、l compiler doesnt produce the code that you wrote.陈渝(清华大学)第 12 讲2020 年 5 月 9 日11/55.Real Hardware/CompilerReal hardware doesnt run the code that you wrote.Real compiler doesnt produce the code that you wrote.陈渝(清华大学)第 12 讲2020 年 5 月 9 日12/55.Real Hardware/CompilerReal hardware doesnt run the code th
8、at you wrote.Real compiler doesnt produce the code that you wrote.Dekkers Algorithm,g+-O2陈渝(清华大学)第 12 讲2020 年 5 月 9 日13/55.C+11 Memory ModelHistoryIn 2011,new versions of the ISO standards for C andC+,informally known as C11 and C+11,wereratified.These standards define a memory model for C/C+Support
9、 for this model has recently become availablein popular compilers(GCC 4.4,Intel C+13.0,MSVC11.0,Clang 3.1).陈渝(清华大学)第 12 讲2020 年 5 月 9 日14/55.C+11 Memory ModelWhy C+11 Memory Model在 C+11 之前,其实是没有定义内存模型的,我们所使用的都是一些处理器/编译器暴露的同步原语,比如 GCC 的内联汇编,内建函数之类的,有着不同的实现。C+11 在标准库中引入了 memory model 的意义在于在 High Level
10、 Language 层面实现对在多处理器中多线程共享内存的访问,实现跨编译器,OS 和硬件的差异性。陈渝(清华大学)第 12 讲2020 年 5 月 9 日15/55.C+11 Memory ModelHappens-beforeAn important fundamental concept inunderstanding the memory modelA guarantee that memory writes by one specificstatement are visible to another specific statement陈渝(清华大学)第 12 讲2020 年 5
11、月 9 日16/55.C+11 Memory ModelHappens-beforeint A=0;int B=0;void foo()A=B+1;/(1)B=1;/(2)陈渝(清华大学)第 12 讲2020 年 5 月 9 日17/55.C+11 Memory ModelHappens-before陈渝(清华大学)第 12 讲2020 年 5 月 9 日18/55.C+11 Memory ModelHappens-beforeint A,B;void foo()A=B+1;B=0;陈渝(清华大学)第 12 讲2020 年 5 月 9 日19/55.C+11 Memory ModelHappe
12、ns-beforeGCC 4.6.1$gcc-S-masm=intel foo.c$cat foo.s.moveax,DWORD PTR _B(redo this at home.)addeax,1movDWORD PTR _A,eaxmovDWORD PTR _B,0.陈渝(清华大学)第 12 讲2020 年 5 月 9 日20/55.C+11 Memory ModelHappens-beforeGCC 4.6.1$gcc-O2-S-masm=intel foo.c$cat foo.s.moveax,DWORD PTR BmovDWORD PTR B,0addeax,1movDWORD PT
13、R A,eax.陈渝(清华大学)第 12 讲2020 年 5 月 9 日21/55.C+11 Memory ModelHappens-beforeGCC 4.6.1int A,B;void foo()A=B+1;asm volatile(:memory);B=0;陈渝(清华大学)第 12 讲2020 年 5 月 9 日22/55.C+11 Memory ModelHappens-beforeGCC 4.6.1$gcc-O2-S-masm=intel foo.c$cat foo.s.moveax,DWORD PTR _Baddeax,1movDWORD PTR _A,eaxmovDWORD PT
14、R _B,0.陈渝(清华大学)第 12 讲2020 年 5 月 9 日23/55.C+11 Memory ModelHappens-before/x86#define COMPILER_BARRIER()asm volatile(:memory)/PowerPC#define RELEASE_FENCE()asm volatile(lwsync:memory)=int Value;std:atomic IsPublished(0);void sendValue(int x)Value=x;/-reordering is prevented here!IsPublished.store(1,st
15、d:memory_order_release);陈渝(清华大学)第 12 讲2020 年 5 月 9 日24/55.C+11 Memory Modelstd:atomicx.load(memory order)x.store(T,memory order)Concurrent accesses on atomic locations do not race.The memory order argument specifies orderingconstraints between atomic and non-atomic memoryaccesses in different thread
16、s.陈渝(清华大学)第 12 讲2020 年 5 月 9 日25/55.C+11 Memory ModelIf multiple threads access the same variable concurrently,and at leastone thread modifies it,all threads must use C+11 atomic operations.陈渝(清华大学)第 12 讲2020 年 5 月 9 日26/55.C+11 Memory Modelstd:atomic陈渝(清华大学)第 12 讲2020 年 5 月 9 日27/55.C+11 Memory Mod
17、elstd:atomic陈渝(清华大学)第 12 讲2020 年 5 月 9 日28/55.C+11 Memory Modelstd:memory_order陈渝(清华大学)第 12 讲2020 年 5 月 9 日29/55.C+11 Memory Modelstd:memory_order_seq_cstThere is a total order over all seq cst operations.This order contributes to inter-thread orderingconstraints.陈渝(清华大学)第 12 讲2020 年 5 月 9 日30/55.C+
18、11 Memory Modelstd:memory_order_seq_cst陈渝(清华大学)第 12 讲2020 年 5 月 9 日31/55.C+11 Memory Modelstd:memory_order_seq_cstsequential consistency直观上,读操作应该返回“最后”一次写入的值。在单处理器系统中,“最后”由程序次序定义。在多处理器系统中,我们称之为顺序连贯(sequential consistency,SC).约束条件在每个处理器内,维护每个处理器的程序次序;在所有处理器间,维护单一的表征所有操作的次序。对于写操作 W1,W2,不能出现从处理器 P1 看来,
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 高级操作系统高级操作系统 34 高级 操作系统 34
限制150内