头文件常用枚举类型定义.docx

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1、1.中断号定义typedef enum IRQn/* * * * * *Cortex-M4ProcessorExceptionsNumbers*/NonMaskablelntJRQn*/MemoryManagementJRQnManagement InterruptBusFault IRQn-14,-12,*/UsageFault_IRQn=-10,*/SVCall IRQn*/DebugMonitor_IRQnInterruptPendSV_IRQn*/=4*/ =2SysTick_IRQn=-1,/*! 2 Non Maskable/*! 4 Cortex-M4*/*! 5 Cortex-

2、M4 Bus FaultInterruptMemoryInterrupt/*! 6 Cortex-M4 Usage Fault Interrupt/*! 11 Cortex-M4 SV Call Interrupt/*! 12 Cortex-M4 Debug Monitor/*! 14 Cortex-M4 Pend SV Interrupt/*! 15 Cortex-M4 System Tick Interrupt*/* * * * * *STM32specificInterruptNumbers*/WWDGJRQn*/PVD_IRQnInterruptTAMP_STAMP_IRQn inte

3、rrupts through the EXTI lineRTC_WKUPRQnthe EXTI line=0,=1,*/=2,*/=3,*/FLASH IRQn/*! Window WatchDog Interrupt/*! PVD through EXTI Line detection/*! Tamper and TimeStamp/*!RTC Wakeup interrupt through/*! FLASH globalInterrupt*/RCC IRQn5,RCC globalInterrupt*/EXTIO IRQn6,/*!EXTILineOInterrupt*/EXTI1 IR

4、Qn7,/*!EXTILinelInterrupt*/EXTI2 IRQn8,EXTILine2Interrupt*/EXTI3 IRQn9,EXTILine3Interrupt*/EXTI4 IRQn10,/*!EXTILine4Interrupt_10 uint32_t CSR;Address offset: 0x74 */uint32_t*/10 uint32 t SSCGR;Address offset: 0x80 */_IO uint32_t PLLI2SCFGR;Address offset: 0x84 */ RCC_TypeDef;8. #define_lvolatile*/#e

5、lse#define_lvolatile*/#endif#define_0volatile*/#define_IOvolatile*/*! RCC clock control & status register,RESERVED62;/* !Reserved,0x78-0x7C/*! RCC spread spectrum clock generation register,/*!RCCPLLI2Sconfiguration register,/*!Definesread onlypermissionsconst/*! Defines read only permissions/*!Defin

6、eswrite onlypermissions/*! Defines read / write permissions*/DMAl_StreamO_IRQn*/DMA l_Streaml_IRQn*/DMA l_Stream2_IRQn*/DMA l_St ream3_IRQn*/DMAl_Stream4_IRQn*/DMA l_Stream5_IRQn*/DMA l_St rea m 6_l RQn*/ADC J RQnInterruptsCANl_TX_IRQn*/CANl_RXO_IRQn*/CANl_RXl_IRQn*/CANl_SCE_IRQn*/EXTI9_5_IRQn*/TIMl

7、_BRK_TIM9_IRQn global interrupt/*! TIM1 Update Interrupt and TIM10/*! TIM1 Trigger and Commutation/*! TIM1 Capture Compare Interrupt=11,/*! DMA1 Stream 0 global Interrupt=12,/*!DMA1Stream1globalInterrupt=13,/*!DMA1Stream2globalInterrupt=14,/*!DMA1Stream3globalInterrupt=15,/*!DMA1Stream4globalInterru

8、pt=16,/*!DMA1Stream5globalInterrupt=17,/*!DMA1Stream6globalInterrupt=18,/*! ADC1, ADC2 and ADC3 global=19,/*! CAN1 TX Interrupt=20,/*!CAN1RXOInterrupt=21,/*!CAN1RX1Interrupt=22,/*!CAN1SCEInterrupt=23,/*! External Line9:5 Interrupts=24,/*! TIM1 Break interrupt and TIM9*/TIMl_UP_TIM10_IRQn= 25,global

9、interrupt*/Tl M 1_TRG_COM_TI Mil J RQn= 26,Interrupt and TIM11 global interrupt */TIMl_CCJRQn= 27,*/TIM2 IRQn=28,TIM2globalInterrupt*/TIM3 IRQn=29,TIM3globalInterrupt*/TIM4 IRQn=30,/*!TIM4globalInterrupt*/I2C1 EV IRQn/*! I2C1 EventInterrupt*/I2C1 ER IRQn32,/*! I2C1 ErrorInterrupt*/I2C2 EV IRQn33,/*!

10、 I2C2 EventInterrupt*/I2C2 ER IRQn34,/*! I2C2 ErrorInterruptSPI1 IRQn35,/*! SPI1globalInterrupt*/SPI2 IRQn36,/*! SPI2globalInterrupt*/USART1 IRQn=37,/*!USART1globalInterrupt*/USART2 IRQn=38,/*!USART2globalInterrupt*/USART3 IRQn=39,/*!USART3globalInterrupt*/EXTI15 10 IRQn=40,/*!External Line15:10 Int

11、errupts*/RTC_Alarm_IRQnLine InterruptOTG_FS_WKUP_IRQn line interruptTIM8_BRK_TIM12_IRQn global interruptTIM8_UP_TIM13JRQn global interruptTIM8 TRG COM TIMM= 41,*/= 42,*/=43,*/*/IRQnInterrupt and TIMM global interrupt */ TIM8 CC IRQn*/DMA1 Stream? IRQn*/FSMC IRQn*/SDIO IRQn*/TIM5 IRQn= 44,=45,=46,=47

12、,/*! RTC Alarm (A and B) through EXTI/*! USB OTG FS Wakeup through EXTI/*! TIM8 Break Interrupt and TIM12/*! TIM8 Update Interrupt and TIM13/*! TIM8 Trigger and Commutation/*! TIM8 Capture Compare Interrupt/*! DMA1 Stream7Interrupt=48,=49,=50,/*! FSMC/*! SDIO/*! TIM5globalglobalglobalInterruptInterr

13、uptInterrupt*/SPI3 IRQn/*! SPI3globalInterrupt*/UART4 IRQn=52,/*! UART4globalInterrupt*/UART5 IRQn=53,/*! UART5globalInterrupt*/TIM6 DAC IRQn=54,/*! TIM6 global and DAC1&2underrun error interruptsTIM7 IRQn*/DMA2 StreamO IRQn*/DMA2 Streaml IRQn=55,/*! TIM7 global interrupt=56,/*! DMA2 Stream 0 global

14、 Interrupt=57,/*! DMA2 Stream 1 global Interrupt*/DMA2 Stream? IRQn*/DMA2 Stream3 IRQn*/DMA2 Stream4 IRQn=58,/*!DMA2Stream2globalInterrupt=59,/*!DMA2Stream3globalInterrupt=60,/*!DMA2Stream4globalInterrupt*/ETH IRQn=61,/*! Ethernet global Interrupt*/ETH WKUP IRQn=62,/*! Ethernet Wakeup through EXTIli

15、ne Interrupt*/CAN2_TX_IRQn*/CAN2_RX0_IRQn*/CAN2_RXlJRQn*/CAN2_SCE_IRQn*/OTG_FS_IRQn*/DMA2_Stream5_IRQn*/DMA2_Stream6_IRQn*/DMA2_Stream7_IRQn*/USART6_IRQn*/l2C3_EV_IRQn*/l2C3_ER_IRQn*/OTG_HS_E Pl_OUTJRQn global interruptOTG_HS_EPl_IN_IRQn interruptOTG_HS_WKUP_IRQn=63,/*! CAN2 TX Interrupt=64,=65,=66,

16、=67,/*! CAN2 RXO Interrupt/*! CAN2 RX1 Interrupt/*! CAN2 SCE Interrupt/*! USB OTG FS global Interrupt=68,/*!DMA2Stream5globalinterrupt=69,/*!DMA2Stream6globalinterrupt=70,/*!DMA2Stream7globalinterrupt=71,/*! USART6 global interrupt=72,/*! I2C3 event interrupt=73,/*! I2C3 error interrupt=74,/*! USB O

17、TG HS End Point 1 Out*/=75,/*! USB OTG HS End Point 1 In global=76,/*! USB OTG HS Wakeup through=77,/*! USB OTG HS global=78,/*! DCMI global=79,/*! CRYP crypto global=80,/*! Hash and Rng global=81/*! FPU globalinterrupt interrupt interrupt interrupt interruptEXTI interrupt OTG_HS_IRQn*/DCMIJRQn*/CRY

18、P_IRQn*/HASH_RNGJRQn*/FPUJRQn*/ IRQn_Type;2 ,数据类型定义 typedef int32_t s32; typedef intl6_t sl6;typedef int8_t s8;typedef const int32_t sc32; /* ! Read Only */ typedef const intl6_t scl6; /* ! Read Only */typedef const int8_t sc8; /* ! Read Only */ typedef _IO int32_t vs32;typedef _IO intl6_t vsl6;type

19、def _IO int8_t vs8;typedef _I int32_t vsc32; /*! Read Only */ typedef _I intl6_t vscl6; /*! Read Only */ typedef _I int8_t vsc8; /*! Read Only */typedef uint32_t u32;typedef uintl6_t ul6;typedef uint8_t u8;typedef const uint32_t uc32; /* ! Read Only */ typedef const uintl6_t ucl6; /*! Read Only */ t

20、ypedef const uint8_t uc8; /* ! Read Only */ typedef _IO uint32_t vu32;typedef _IO uintl6_t vul6;typedef _IO uint8_t vu8;typedef _I uint32_t vuc32; /*! Read Only */typedef _I uintl6_t vucl6; /*! Read Only */typedef _I uint8_t vuc8;/*! Read Only */参考一下的定义typedeftypedeftypedeftypedeftypedeftypedeftyped

21、eftypedefsignedsigned short signed signedchar int8_t;int intl6_t;int int32_t;int64 int64 t;/* exact-width unsigned integer types */typedef unsignedchar uint8_t;typedef unsigned shortint uintl6_t;typedef unsignedint uint32_t;typedef unsigned_int64 uint64_t;/* 7.18.1.2 */* smallest type of at least n

22、bits */* minimum-width signed integer types */typedef unsigned typedef unsigned short typedef unsigned typedef unsigned/* 7.18.1.3 */typedef unsigned typedef unsigned short typedef unsigned typedef unsigned/* 7.18.1.3 */char uint_least8_t;int uint Ieastl6 t;int uint Ieast32 t;MB，int64 uint_least64_t

23、;/* minimum-width unsigned integer types */typedefsignedchar int_least8_ttypedefsigned shortint int Ieastl6 t;typedefsignedint int_least32_typedefsigned_int64 intjeast64_/* fastest minimum-width signed integer types */typedefsignedint int_fast8_t;typedefsignedint int_fastl6_t;typedefsignedint int_fa

24、st32_t;typedefsigned_int64 int_fast64_t;/* fastest minimum-width unsigned integer types */typedef unsigned typedef unsigned typedef unsigned typedef unsignedtypedef unsigned typedef unsigned typedef unsigned typedef unsignedint uint fa st 8 t;int uint_fastl6_t;int uint_fast32_t;int64 uint fa st 64 t

25、;/* 7.18.1.4 integer types capable of holding object pointers */typedef signedint intptr_t；typedef unsignedint uintptr_t;/* 7.18.1.5 greatest-width integer types */typedef signed_int64 intmax_t;typedef unsigned_int64 uintmax_t;3 .标志状态类型定义typedef enum RESET = 0, SET = !RESET FlagStatus, ITStatus;4 .功

26、能状态使能类型定义FonctionStatetypedef enum DISABLE = 0, ENABLE = (DISABLE FunctionalState;ftdefine IS_FUNCTIONAL_STATE(STATE) (STATE) = DISABLE) | | (STATE) = ENABLE).ADC类型定义typedef struct(_10 uint32_t SR;0x00 */_IO uint32_t CR1;0x04 */_IO uint32_t CR2;0x08 */_IO uint32_t SMPR1;OxOC */_IO uint32_t SMPR2;0x1

27、0 */_IO uint32_t J0FR1;*/IO uint32 t J0FR2;*/_IO uint32_t J0FR3;*/_IO uint32_t J0FR4;*/_IO uint32_t HTR;0x24 */_IO uint32_t LTR;0x28 */_IO uint32_t SQR1;0x2C */IO uint32 t SQR2;0x30 */_IO uint32_t SQR3;0x34 */_IO uint32_t JSQR;0x38*/_IO uint32_t JDR1;/*! ADC status register,/*! ADC control register

28、1,/*! ADC control register 2,/*! ADC sample time register 1,/*! ADC sample time register 2,Address offset:Address offset:Address offset:Address offset:Address offset:/*! ADC injectedchanneldataoffsetregister1,Addressoffset:0x14/*! ADC injectedchanneldataoffsetregister2,Addressoffset:0x18/*! ADC inje

29、ctedchanneldataoffsetregister3,Addressoffset:OxlC/*! ADC injected channel data offset register 4, Address offset: 0x20/*! ADC watchdog higher threshold register, Address offset:/*! ADC watchdog lower threshold register, Address offset:/*! ADC regular sequence register 1, /*! ADC regular sequence reg

30、ister 2, /*! ADC regular sequence register 3, /*! ADC injected sequence register;/*! ADC injected data register 1,Address offset:Address offset:Address offset:Address offset:Address offset:Address offset:Address offset:Address offset:Address offset:Address offset:0x3C */_10 uint32_t JDR2; /*! ADC in

31、jected data register 2, 0x40 */_10 uint32_t JDR3; /*! ADC injected data register 3, 0x44 */_10 uint32_t JDR4; /*! ADC injected data register 4, 0x48 */_10 uint32_t DR; /*! ADC regular data register, 0x4C */ ADC_TypeDef;6 .GPIO类型定义Address offset:Address offset:Address offset:Address offset:typedef st

32、ruct_IO uint32_t MODER;/*! GPIO port mode register,Address offset:*/0x0010 uint32 t OTYPER;/_IO uint32_t OSPEEDR;/_IO uint32_t PUPDR;/_IO uint32_t IDR;/_10 uint32_t ODR;/*! GPIO port output type register,/*! GPIO port output speed register,/*! GPIO port pull-up/pull-down register,/*! GPIO port input

33、 data register,/*! GPIO port output data register,Address offset: 0x04Address offset: 0x08Address offset: OxOCAddress offset: 0x10Address offset: 0x14_IO*/_IO*/_IO*/10uintl6 t BSRRL;uintl6_t BSRRH;uint32_t LCKR;uint32_t AFR2;/*! GPIO port bit set/reset low register,/*! GPIO port bit set/reset high r

34、egister,/*! GPIO port configuration lock register,/*! GPIO alternate function registers,AddressAddressAddressoffset:offset:offset:0x18OxlAOxlCAddress offset:0x20-0x24 */ GPIO_TypeDef;7 .RCC类型定义 typedef struct_10 uint32_t CR;Address offset: 0x00 */_IO uint32_t PLLCFGR;Address offset: 0x04 */_IO uint3

35、2_t CFGR;Address offset: 0x08 */_10 uint32_t CIR;Address offset: OxOC */*!/*! RCC/*! RCCRCC clock controlPLL configurationclock configuration/*! RCC clock interruptregister,register,register,register,_IO uint32_t AHB1RSTR;Address offset: 0x10 */_IO uint32_t AHB2RSTR;Address offset: 0x14 */10 uint32

36、t AHB3RSTR;Address offset: 0x18 */uint32_t*/_IO uint32_t APB1RSTR;Address offset: 0x20 */_IO uint32_t APB2RSTR;Address offset: 0x24 */uint32_t*/10 uint32 t AHB1ENR;Address offset: 0x30 */_IO uint32_t AHB2ENR;Address offset: 0x34 */_IO uint32_t AHB3ENR;Address offset: 0x38 */uint32_t*/_IO uint32_t AP

37、B1ENR;Address offset: 0x40 */10 uint32 t APB2ENR;Address offset: 0x44 */uint32_t*/_IO uint32_t AHB1LPENR;register, Address offset: 0x50 */_IO uint32_t AHB2LPENR;register, Address offset: 0x54 */_IO uint32_t AHB3LPENR;register, Address offset: 0x58 */ uint32_t*/IO uint32 t APB1LPENR;register, Address

38、 offset: 0x60 */_IO uint32_t APB2LPENR;register, Address offset: 0x64 */ uint32_t*/_IO uint32_t BDCR;Address offset: 0x70 */*!/*!/*!RESERVEDO;/*!RESERVED12;/*!/*!RESERVED2;/*! RCC/*! RCCRESERVED32;RCC AHB1RCCRCCRCCRCCRCCRCCRCCRCCAPB1APB2/*!/*!AHB1AHB2AHB3APB1APB2/*!AHB1AHB2AHB3RCC AHB2RCC AHB3RESERV

39、ED4;/*! RCC APB1/*! RCC APB2peripheralperipheralperipheralresetresetreset/*! Reserved,peripheral resetperipheral resetregister,register,register,OxlCregister,register,Reserved, 0x28-0x2Cperipheralperipheralperipheralclockclockclock*! Reserved,peripheralperipheralregister,register,register,0x3Cclock

40、enableclock enableReserved,peripheral clock enableperipheral clock enableperipheral clock enableperipheral clock enableperipheral clock enableRESERVED52;inininlowlowlowregister,register,0x48-0x4CpowerpowerpowerReserved,in lowin low/*! Reserved,modemodemode0x5Cpowerpowermodemode0x68-0x6C/*! RCC Backup domain control register,