2022年毕业设计方案说明书外文文献及翻译 .docx

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1、精选学习资料 - - - - - - - - - 外文文献：Embedded Systems Design using the TI MSP430 Series up to larger 60k ROM, 2k RAM, with prices in the $10range devices. Currently, there are at least 40 flavors available, with more being added regularly. The devices are split into three families: the MSP430x3xx, which is

2、 a basic unit, the MSP430x1xx, which is a morefeature-rich family, and the MSP430x4xx, which is similar to the 1xx, witha built in LCD driver. You will find these referred to as 1xx, 3xx, and 4xxdevices throughout this book. Part Numbering Convention Part numbers for MSP430 devices are determined ba

3、sed on their capabilities. All device part numbers follow the following template: MSP430M tFa F bM c1 / 20 名师归纳总结 - - - - - - -第 1 页,共 20 页精选学习资料 - - - - - - - - - M: Memory Type C: ROM F: Flash P: OTP E: EPROM for developmental use. There are few of these. F a, F b: Family and Features 10, 11: Basi

4、c 12, 13: Hardware UART 14: Hardware UART, Hardware Multiplier 31, 32: LCD Controller 33: LCD Controller, Hardware UART, Hardware Multiplier 41: LCD Controller 43: LCD Controller, Hardware UART 44: LCD Controller, Hardware UART, Hardware Multiplier M c: Memory Capacity 0: 1kb ROM, 128b RAM 1: 2kb RO

5、M, 128b RAM 2: 4kb ROM, 256b RAM 3: 8kb ROM, 256b RAM 4: 12kb ROM, 512b RAM 5: 16kb ROM, 512b RAM 6: 24kb ROM, 1kb RAM 7: 32kb ROM, 1kb RAM 8: 48kb ROM, 2kb RAM 9: 60kb ROM, 2kb RAM Example: The MSP430F435 is a Flash memory device with an LCDcontroller, a hardware UART, 16 kb of code memory, and 512

6、 bytes of RAM. The part numbering scheme described above is a bit fragmented. Thereare common features not consistently represented type of ADC, number oftimers, etc, and there are some other 2 / 20 名师归纳总结 - - - - - - -第 2 页,共 20 页精选学习资料 - - - - - - - - - inconsistencies for example, the 33family ha

7、s the multiplier, but the 13 and 43s do not. I would recommendagainst selecting parts based on their numbering scheme. Rather, once youhave a vague idea of your requirements, go to the TI website www.TI.com,and use their parametric sort feature. Architecture: CPU and Memory As discussed in chapter 1

8、, the MSP430 utilizes a 16-bit RISC architecture, which is capable of processing instructions on either bytes or words. TheCPU is identical for all members of the 430 family. It consists of a 3-stageinstruction pipeline, instruction decoding, a 16-bit ALU, four dedicated-useregisters, and twelve wor

9、king or scratchpad registers. The CPU is connected to its memory through two 16-bit busses, one for addressing, and theother for data. All memory, including RAM, ROM, information memory, special function registers, and peripheral registers are mapped into a single, contiguous address space. This arc

10、hitecture is unique for several reasons. First, the designers at Texas Instruments have left an awful lot of space for future development. Almost half the Status Register remains available for future growth, roughly half of the peripheral register space is unused, and only six of the sixteen availab

11、le special function registers are implemented. Second, there are plenty of working registers. After years of having one or two workingregisters, I greatly enjoyed my first experience with the twelve 16-bit CPU scratchpads. Theprogramming style is slightly different, and can be much more efficient, e

12、specially in the hands of a programmer who knows how to use this feature to its fullest. Third, this architecture is deceptively straightforward. It is very flexible, and the addressing modes are more complicated than most other smallprocessors. But, beyond that, this architecture is simple, efficie

13、nt and clean. There are twobusses, a single linear memory space, a rather vanilla processor core, and all peripherals are memory-mapped. CPU Features The ALU 3 / 20 名师归纳总结 - - - - - - -第 3 页,共 20 页精选学习资料 - - - - - - - - - The 430 processor includes a pretty typical ALU arithmetic logic unit. The ALU

14、 handlesaddition, subtraction, comparison and logical AND, OR, XOR operations. ALU operationscan affect the overflow, zero, negative, and carry flags. The hardware multiplier, which is notavailable in all devices, is implemented as a peripheral device, and is not part of the ALU seeChapter 6. Workin

15、g Registers The 430 gives the developer twelve 16-bit working registers, R4 through R15. R0 through R3 are used for other functions, as described later. They are used for register mode operations see Addressing Modes, Chapter 8, which are much more efficient than operations which require memory acce

16、ss. Some guidelines for their use: Use these registers as much as possible. Any variable which is accessed often shouldreside in one of these locations, for the sake of efficiency. Generally speaking, you may select any of these registers for any purpose, either dataor address. However, some develop

17、ment tools will reserve R4 and R5 for debuginformation. Different compilers will use these registers in different fashions, as well.Understand your tools. Be consistent about use of the working registers. Clearly document their use. I havecode, written about 8 months ago, that performs extensive ope

18、rations on R8, R9, andR15. Unfortunately, I dont know today what the values in R8, R9 and R15 represent.This was code I wrote to quickly validate an algorithm, rather than production code, so Ididnt document it sufficiently. Now, it is relative gibberish. Dont let this happen to you.No matter how ob

19、vious or trivial register use seems, document it anyway. Constant Generators R2 and R3 function as constant generators, so that register mode may be used instead ofimmediate mode for some common constants. R2 is a dualuse register. It serves as the Status Register, as well. Generated constants inclu

20、de some common single-bit values 0001h, 0002h, 0004h, and 0008h, zero 0000h, and an all 1s field 0FFFFh. Generation is based on the WS value in the instruction word, and is described by the table below. WS value in R2 value in R3 00 0000h 01 0 absolute mode 0001h 4 / 20 名师归纳总结 - - - - - - -第 4 页,共 2

21、0 页精选学习资料 - - - - - - - - - 10 0004h 0002h 11 0008h 0FFFFh Program Counter The Program Counter is located in R0. Since individual memory location addresses are 8-bit, but all instructions are 16 bit, the PC is constrained to even numbers i.e. the LSB of the PC is always zero. Generally speaking, it

22、is best to avoid direct manipulation of the PC. One exception to this rule of thumb is the implementation of a switch, where the codejumps to a spot, dependent on a given value. I.e., if value=0, jump to location0, if value=1,jump to location1, etc. This process is shown in Example 3.1. Example 3.1

23、Switch Statement via Manual PC Control Mov value,R15 ；put the switch value into R15 Cmp R15,#8 ；range checking Jge outofrange ；if R157,do not use PC switch Cmp #0,R15 ；more range checking Jn outofrange ；Rla R15 ；multiply R15 by two,since PC is always even Rla R15 ；double R15again,sincesymbolic jmp i

24、s 2 words long Add R15,PC ；PC goes to proper jump Jmp value0 Jmp value1 Jmp value2 Jmp value3 Jmp value4 Jmp value5 Jmp value6 Jmp value7 Outofrange Jmp RangeError This is a relatively common approach, and most C compilers will implement switch statements with something similar. When implementing th

25、is manually i.e., in assembly 5 / 20 名师归纳总结 - - - - - - -第 5 页,共 20 页精选学习资料 - - - - - - - - - language, the programmer needs to keep several things in mind: Always do proper range checking. In the example, we checked for conditionsoutside both ends of the valid range. If this is not performed correc

26、tly, the code canjump to an unintended location. Pay close attention to the addressing modes of the jump statements. The second doubling of R15, prior to the add statement, is added because the jump statement requires two words when symbolic mode addressing is used. Be careful that none of your inte

27、rrupt handlers have the potential to affect your value register R15 in the example. If the interrupt handler needs to use one of these registers, the handler needs to store the value to RAM first. The most common procedure is to push the register to the stack at the beginning of the ISR, and to pop

28、the register at the end of the ISR. See Example 3.2. Example 3.2 Push/Pop Combination in ISR Timer_A_Hi_Interrupt Push R12 ；We will use R12 Mov P1IN,R12 ；use R12 as we please Rla R12 Rla R12 Mov R12&BAR ；Done with R12 Pop R12 ；Restore previous value to R12 Reti ；return from interrupt ORG 0FFF0h DW T

29、imer_A_Hi_Interrupt Status Register The Status Register is implemented in R2, and is comprised of various system flags. The flags are all directly accessible by code, and all but three of them are changed automatically by the processor itself. The 7 most significant bits are undefined. The bits of t

30、he SR are: . The Carry Flag C Location: SR0 the LSB Function: Identifies when an operation results in a carry. Can be set or cleared by software, 6 / 20 名师归纳总结 - - - - - - -第 6 页,共 20 页精选学习资料 - - - - - - - - - or automatically. 1=Carry occurred 0=No carry occurred .The Zero Flag Z Location: SR1 Func

31、tion: Identifies when an operation results in a zero. Can be set or cleared by software, or automatically. 1=Zero result occurred 0=Nonzero result occurred . The Negative Flag N Location: SR2 Function: Identifies when an operation results in a negative. Can be set or cleared by software, or automati

32、cally. This flag reflects the value of the MSB of the operation result Bit 7 for byte operations, and bit15 for word operations. 1=Negative result occurred 0=Positive result occurred . The Global Interrupt Enable GIE Location: SR3 Function: Enables or disables all maskable interrupts. Can be set or

33、cleared by software, or automatically. Interrupts automatically reset this bit, and the reti instruction automatically sets it. 1=Interrupts Enabled 0=Interrupts Disabled . The CPU off bit CPUOff Location: SR4 Function: Enables or disables the CPU core. Can be cleared by software, and is reset by en

34、abled interrupts. None of the memory, peripherals, or clocks are affected by this bit. This bit is used as a power saving feature. 1=CPU is on 0=CPU is off 7 / 20 名师归纳总结 - - - - - - -第 7 页,共 20 页精选学习资料 - - - - - - - - - . The Oscillator off bit OSCOff Location: SR5 Function: Enables or disables the

35、crystal oscillator circuit LFXT1. Can be cleared by software, and is reset by enabled external interrupts. OSCOff shuts down everything, including peripherals. RAM and register contents are preserved. This bit is used as a power saving feature. 1=LFXT1 is on 0=LFXT1 is off . The System Clock Generat

36、or SCG1,SCG0 Location: SR7,SR6 Function: These bits, along with OSCOff and CPUOff define the power mode of the device. .The Overflow Flag V Location: SR8 Function: Identifies when an operation results in an overflow. Can be set or cleared by software, or automatically. Overflow occurs when two posit

37、ive numbers are added together, and the result is negative, or when two negative numbers are added together, and the result is positive. 1=Overflow result occurred 0=No overflow result occurred Four of these flags Overflow, Negative, Carry, and Zero drive program control, via instructions such as cm

38、p compare and jz jump if Zero flag is set. You will see these flags referred to often in this book, as their function represents a fundamental building block. The instruction set is detailed in Chapter 9, and each base instruction description there details the interaction between flags and instructi

39、ons. As a programmer, you need to understand this interaction. Stack Pointer The Stack Pointer is implemented in R1. Like the Program Counter, the LSB is fixed as a zero value, so the value is always even. The stack is implemented in RAM, and it is common practice to start the SP at the top highest

40、valid value of RAM. The push command moves the SP down one word in RAM SP=SP-2, and puts the value to be pushed at the new SP. Pop does 8 / 20 名师归纳总结 - - - - - - -第 8 页,共 20 页精选学习资料 - - - - - - - - - the reverse. Call statements and interrupts push the PC, and ret and reti statements pop the value f

41、rom the TOS top of stack back into the PC. I have one simple rule of thumb for the SP: leave it alone. Set the stack pointer as part of your initialization, and dont fiddle with it manually after that. As long as you are wary of two stack conditions, the stack pointermanages itself. These two conditions are: Asymmetric push/pop combinations. Every push should have a pop. If you push a bunch of variables, and fa