嵌入式项目开发过程讲课教案.ppt

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1、嵌入式项目开发过程嵌入式项目设计的各个阶段（图）嵌入式项目设计的七个具体阶段n产品定义n软件与硬件的划分n迭代与实现n详细的硬件与软件设计n硬件与软件集成n产品测试与发布n持续维护与升级嵌入式项目开发过程中使用的工具n参见PDF文档中的Figure 1.2嵌入式项目设计生命周期（一）产品定义n工程师追求卓越的功能和性能n浪费时间和资源n决策层早期一般不允许工程师接触客户n损失了一些有用的建议和观点n理想的客户研究访问n首席：市场营销；第二成员：记录与提问n其他技术人员：参与探讨并形成产品蓝图n列出必做适宜清单，找到设计产品的共同蓝图嵌入式项目设计生命周期（二）硬件与软件的划分n观点：软硬件是可

2、以互相替换的n如：浮点运算与浮点处理器（FPU）等n两种不同的划分策略n优化处理器能力和软件n通过ASIC设计找到解决途径n划分中需要考虑的许多需求n价格低、性能领先、市场竞争、知识产权等nCPU的选择将影响划分决策和开发工具选择嵌入式项目设计生命周期（三）迭代与实现n迭代与实现阶段的主要特点：n主要障碍可能还是在软硬件的详细划分上n设计约束被深刻理解和建模n保留软硬件划分之间的余地n软硬件设计人员之间的迭代n结构体系模拟器：Simulatorn评估板或开发板：Evaluation Boardn目的：减小设计阶段后期风险嵌入式项目设计生命周期（四）详细的硬件与软件设计文档管理n这里不详细讨论软

3、硬件设计问题n大部分同学在其他课程中学到的C/C+/JAVA编程技术、数字设计和微处理器知识使他们有足够的机会解决设计中遇到的问题n文档管理与质量控制n设计复用和可视化n减小设计修改成本n有助于测试和质量控制嵌入式项目设计生命周期（五）硬件与软件集成nNot a easy ProblemnBig Endian/Little Endian引发的问题n调试过程及实时系统调试方法带来的一些问题等n嵌入式系统设计中软硬件集成的理想状态n由第一个硬件原型、应用软件、驱动代码、操作系统设计出完美的系统n没有致命错误n没有飞线n不用重新设计ASIC或FPGAn没有太多的软件设计修改嵌入式项目设计生命周期（六

4、）产品测试与发布n嵌入式产品测试具有特殊的意义n人们或许可以容忍PC偶然死机，但是核电站报警系统？！导弹控制系统？！nPC外围硬件Is there any problem with you?n测试的目的n不仅是确信软件不会在关键时刻崩馈n还必须查明是否在运行时能接近最优性能，尤其是用高级语言编写或多个开发人员编写的程序n每个微小的错误都可能是致命的n如轻微内存泄漏，长时间运行才能发现的问题等嵌入式项目设计生命周期（七）产品维护和升级n产品维护的模式n维护/支持小组!设计小组n维护详细文档经验技巧上一代产品n产品升级的巨大代价n理解原设计人员的思路与代码n反向逆推并改进原始设计小组的工作n需要非

5、凡的技艺或强大的反向设计工具n否则，不如开始新的设计，这是原供应商和生产上所不愿意看到的主要内容n嵌入式设计生命周期n选择过程n划分决策n详细的硬件与软件设计n嵌入式硬件开发过程n嵌入式软件开发过程n软硬件协同设计过程n开发、调试环境与工具选择过程处理器平台n选择处理器是一个复杂的工作，它不仅是一个简单的“优化”问题，必须通过四道关键测试：n是否便于实现n是否能够提供足够的性能n是否有合适的操作系统支持n是否有大量合适的开发工具（和设计资源）支持n其他因素可能会影响这种选择n上市时间、企业对特定开发商的偏好或承诺等How do we choose microprocessor?PowerBud

6、getCost ofGoodsReal-timeConstraintsLegacyCodePerformanceTime toMarketLandminesTool SupportnBrute force method of improving performancenBottleneck could be in software design or compiler!nFaster isnt always betternPerformance Clock speed nTrade-off:nAs clock speed energy nMemory costs increasenOther

7、peripheral devices will cost moreClock SpeedEvaluating processor performancenClock speed:but instructions per cycle may differnInstructions/sec:but work per instruction may differnDhrystone:Synthetic benchmark,developed in 1984nSPEC:realistic benchmarks,but oriented to desktopsnEEMBC EDN Embedded Be

8、nchmark Consortium,www.eembc.orgnSuites of benchmarks:automotive,consumer electronics,networking,office automation,telecommunicationsvon Neumann ArchitecturememoryCPUPCaddressdataIRADD r5,r1,r3200200ADD r5,r1,r3Harvard architectureCPUPCdata memoryprogram memoryaddressdataaddressdatavon Neumann vs.Ha

9、rvardnHarvard cant use self-modifying code.nHarvard allows two simultaneous memory fetches.nMost DSP use Harvard architecture for streaming data:ngreater memory bandwidth;nmore predictable bandwidth.ARM vs.SHARCnARM7 is von Neumann architecturenWe will concentrate on ARM7nARM9 is Harvard architectur

10、enSHARC is modified Harvard architecture.nOn chip memory(1Gbit)evenly split between program memory(PM)and data memory(DM)nProgram memory can be used to store some data.nAllows data to be fetched from both memory in paralleluP PerformancenWidth of data path nperformance (Width of Data Path)2 nThe mos

11、t general categorization of processor performancenTypical data bus widths:4,8,16,32,64,128 bits widenWider data busses-greater data processing capabilitynData bus width trade-off,the wider data path:nIs more complex to designnTakes up more room on PC boardsnGenerates greater amounts of energynRequir

12、es more costly memory designsnIs not compatible with existing hardwareMore on data path widthnData path width generally determines functionalityn4,8 bits-Appliances,modems,simple applicationsn16 bits-Industrial controllers,automotiven32 bits-Telecomm,laser printers,high-performance appsn64 bits-PCs,

13、UNIX workstations,gamesn128,256 bits(VLIW)-Next generationnInternal and external data paths may differ in sizenNarrower memory is more economicalnMC68000:32-bit internal/16-bit externalnMC68008:32-bit internal/8-bit externaln80C188:16-bit internal/8-bit externalnRemember:An 8-bit processor can do al

14、most everything a 64-bit processor can do,it will just take longer to accomplishProcessor Micro-architecturenOn-chip instruction/data cache,how big?nPipelinesnSuperscalar/VLIWnTrade-off-high performance costs money,powernAddress bus designnAddress bus width:16-36 bits nMultiplexed,synchronous,asynch

15、ronousnProcessor type:CISC,RISC,DSPnWhat is the nature of the algorithm to implement?nControl rich:CISCnData rich:RISCnData transforms and mathematical processing:DSPMore on address bus widthnThe amount of externally accessible memory is defined as the Address Space of the processornCan vary from 1K

16、B for simple microcontrollers to over 60 GB in high performance processorsnSize of the address space doesnt mean that you have that much memory,it only means that the capabilities exist to directly access itnProcessors with smaller address spaces can still manipulate larger memory arrays with techni

17、ques such as PagingnSpecial memory or I/O location used to swap in and out memory pagesnExample:An 8-bit Z80 processor with a 16-bit address bus(64K)can address a 1Mbyte address space by swapping between one of 16,64Kbyte,memory pagesnCombine CISC,RISC and DSP in a single designnTight coupling or lo

18、ose couplingnArchitecturenCode design,compiler capabilitiesnDebug tool availabilitynSystem simulation toolsSingle or Multiple processorsnMicroprocessor or microcontroller?nReview:nA microprocessor contains the basic CPU functionality,and morenA microcontroller combines the CPU core with peripheral d

19、evicesnThe microprocessor is usually the leading edge of performance nLowest level of integrationnHighest costnHigher levels of integration implynLower system costsnGreater reliability nLess powernFasternHigher processor costnAs uP matures the core moves into the uC familiesIntegration of functionsR

20、AMROMFLASHTimersDMA$100KNRECoprocessorCacheA/D ConverterSerial PortsEthernet Parallel PortsWatchdogLCD ControllerFLASHPCI Bus BridgeCPU CoreReal-timeClockCSSAP490B主要内容n嵌入式设计生命周期n选择过程n划分决策n详细的硬件与软件设计n嵌入式硬件开发过程n嵌入式软件开发过程n软硬件协同设计过程n开发、调试环境与工具划分决策n软件与硬件的双重性n软件与硬件的分离：基于开发成本和性能的决策n新的硬件描述语言：HDLHandel-Cn协同设

21、计过程Hardware/Software PartitioningnDefinitionnThe process of deciding,for each subsystem,whether the required functionality is more advantageously implemented in hardware or softwarenGoalnTo achieve a partition that will give us the required performance within the overall system requirements(in size,

22、weight,power,cost,etc.)nThis is a multivariate optimization problem that when automated,is an NP-hard problemHW/SW Partitioning IssuesnPartitioning into hardware and software affects overall system cost and performance nHardware implementationnProvides higher performance via hardware speeds and para

23、llel execution of operationsnIncurs additional expense of fabricating ASICsnSoftware implementationnMay run on high-performance processors at low cost(due to high-volume production)nIncurs high cost of developing and maintaining(complex)softwarePartitioning ApproachesnStart with all functionality in

24、 software and move portions into hardware which are time-critical and can not be allocated to software (software-oriented partitioning)nStart with all functionality in hardware and move portions into software implementation (hardware-oriented partitioning)主要内容n嵌入式设计生命周期n选择过程n划分决策n详细的硬件与软件设计n嵌入式硬件开发过

25、程n嵌入式软件开发过程n软硬件协同设计过程n开发、调试环境与工具软硬件设计过程中的文档管理n需求分析文档（产品定义阶段）n总体方案设计（选择过程和软硬件划分）n概要设计文档（软硬件初步设计）n详细设计文档（软硬件详细设计）n测试需求文档（模块测试及联调准备）n系统测试报告（测试小组）n使用说明文档/源程序注释总体方案设计n项目概述（来自需求分析文档）n功能与指标描述（来自需求分析文档）n系统外部接口描述n系统软硬件设计框架（选择过程和划分决策）n软硬件模块化设计概要n功能、接口n时间与进度安排（甘特图）n产品成本估算n研制经费需求甘特图时间2002/12/1任务2003/1/12003/2/1

26、2003/3/12003/4/12003/5/1技术方案设计系统软件构建原理图及PCB设计春节BSP及设备驱动程序PCB制板及硬件调试IP Core及FPGA设计与仿真系统联调、设计验证产品现场测试设计完善图图4 项目研制进度与计划安排项目研制进度与计划安排模块化设计n功能描述n接口描述：硬件接口与软件参数n设计流图n自然语言n流程框图n原理框图n状态流图UML：统一建模描述语言状态流图软硬件统一描述方式State Diagram of Recording a MessageCheck the number of messagesTurn on the Warning Turn off the

27、 warningGenerate memory address and record message&inc message counterDelete the first message and decrement message counterHang UpMessage counter=24Message Counter=30Memory Page is fullReset Warning Message=1-23,24-29Memo Button主要内容n嵌入式设计生命周期n选择过程n划分决策n详细的硬件与软件设计n嵌入式硬件开发过程n嵌入式软件开发过程n软硬件协同设计过程n开发、调试

28、环境与工具嵌入式软件开发环境C or C+Source FileC or C+CompilerIncludeFilesSourceListingAssemblySource FileAssemblerSourceListingRelocatable ObjectModuleCreate UserLibrary(optional)LibrarianUser LibraryLibraryDirectoryListingLinkerLinkerCommandFileRelocatable ObjectModuleLink MapAbsolute ObjectModuleDeviceProgramme

29、rTargetDevelopmentSystemDebugging ToolsetnInstruction Set Simulator(ISS)nDebug MonitornROM EmulatornLogic AnalyzernIn-Circuit Emulator(ICE)nJoint Test Action Group(JTAG)Debugging embedded systemsnChallenges:ntarget system may be hard to observe;ntarget may be hard to control;nmay be hard to generate

30、 realistic inputs;nsetup sequence may be complex.Instruction Level SimulatornHost based software that simulates the functionality and instruction set of the target processornTwo typesnFunctionality-accuratenImplements only instruction setnCycle-accuratenMaintain cycle-by-cycle accuracy of processor,

31、including cache,pipeline,and memory behaviornUseful in early stage of the projectnDisadvantage:nNo simulation of peripheralsnCannot model interaction with I/O devicesRemote DebuggernFront-end runs on host computer and provides user interfacenBackend runs on target processor and communicates with the

32、 front-end over communication linknBackend is known as debug monitor and provides low level control of target processorDebug monitornA monitor program residing on the target ROM provides basic debugger functionsnRead register xnModify register ynRead n bytes of memory starting at addressnModify data

33、 at addressnRun to breakpointnSingle stepnLoad codenDebugger should have minimal footprint in memory.nUser program must be careful not to destroy debugger programDebug monitor(Contd.)SYSTEM ROM CODE PARTITION0 x00000 0 xFFFFFPower on reset codeSerial PortInt.VectorSerial PortISRDebugKernelSoftwarede

34、bug trapvectorApplicationProgramHOST-BASED DEBUGGER PROGRAM -Knowledge of source files -Knowledge of object files Symbol Table Cross reference filesSERIAL COMM LINK1023012Debug monitors:AdvantagesnLow cost:$0 to 200 channels,1GHz data ratesnCan observe entire digital system at the same timenCan be u

35、sed in conjunction with instrumented code for real time measurements in cached processorsLogic Analyzer:DisadvantagesnCan be very expensivenStrictly passive,cannot provide control of processornComplexnNot well-integrated into software design environmentnMust combine with other tools for complete sol

36、utionnCached processors cannot be observed nCode must be instrumented if cache is not visibleIn-circuit emulators(ICE)nAn ICE provides an integration of the most important functions required to debug embedded systemsnMicroprocessor run Control(Debug monitor)nMemory substitution(ROM Emulator)nReal Ti

37、me Trace(Logic Analyzer)nA microprocessor in-circuit emulator is a specially-instrumented microprocessor.A typical engineer with emulatorTypical engineerEmulatorTarget systemHost ComputerICE(Contd.)Target systemProbe head contain emulation microprocessor -Substitutes for,or disables target microproc

38、essor -Contains run control circuitry and cable buffers -May contain memory mapping hardwareMain chassis -Contains emulation(overlay memory)-Trace analysis hardware and trace memory -Performance analysis hardware(-Power supply -Control and communicationsHost computer runs emulator control software -

39、Provides run control -Displays real time trace at source level -Loads overlay memory with object code -High-speed link to emulation chassisICE(Contd.)nRun controlnSimilar to the functionality of a software debug kernelnPeek/poke memorynModify registersnSingle stepnSet breakpointsnDisassemble memory

40、codenDownload codeICE(contd.)nOverlay memorynSimilar to functionality of ROM emulatornProvides overlay(substitution)memory for target system memorynEntire memory space can be“mapped”to provide memory regions in anywhere in the address space of target processornEmulation memory interspersed with targ

41、et system memorynEmulation memory can be assigned special attributesnROM(no writes allowed)nGuarded(break on write)nCode space or data spacenShared memory(simulated I/O)ICE AdvantagesnPremier tool for embedded system hw/sw integration nProvides all the functionality needed for connectivity,observati

42、on and control of an embedded systemnControl of the microprocessor is guaranteed,independent of the state of target system hardwarenOverlay memory substitutes for the target system ROM to permit trace of code executionnTraces program flownFilter out extraneous bus activity(pre-fetches)nSpecial circu

43、itry can display cache activitynTight integration through single user interface on hostnCan provide very unique and valuable measurements ICE:DisadvantagesnNot always most cost-effective solutionnCan be extremely expensive($20K)nCostly to equip a team of designersnNew emulator often required for new

44、 processor or upgradenViewed as a complex and fragile instrumentnAvailability usually lags early siliconnCannot easily track microcontroller variantsnConnectivity to surface-mounted processors is very difficult,and the problem is getting worsenViewing cached program activity can be very difficult (o

45、r,at worst)impossible nNot the tool of choice for code design at the upper levels of abstraction Joint Test Action Group(JTAG)nOriginally developed as a board test methodology to replace“bed of nails”testersnPC boards tested on complex machines with dense array of point contacts(bed of nails)to conn

46、ect to every node on the boardnNode is a shared interconnection between board componentsnLink outputs of all digital devices on PC board with individual bits of one long shift registernCan observe whether any circuit node is stuck high,low,shorted or disconnectedJTAG LoopEach JTAG cell“sniffs”the st

47、ate of the corresponding output bit of the ICJTAG bit stream inJTAG bit stream outBit stream forms one long shift-registerPC BoardJTAG ConnectorJTAG can be a debug protocolnLink all the internal registers and other important circuit blocks in a JTAG loopnProvide capability to drive output as well as

48、 sniff itnAdd internal debug registers accessible via JTAGnCan provide a low-cost standard debug interface,independent of chip variationsnGreat for silicon vendors and end usersnOne low-cost($100 tool)supports any JTAG-compatible deviceJTAG-based debug kernelProcessor CoreProgram Counter-PCRegister

49、R1Register R2Register RnAddr Bus InterfaceData Bus InterfaceStatus Bus InterfaceJTAG Control State MachineJTAG inClock inJTAG out“SPECIAL”REGISTER SETMore on JTAGnDe-facto standard for on-chip debugnVery cost effectivenCan be re-programmed to support multiple processor familiesnTypically priced unde

50、r$1000 nDebug capability is defined by features of debug corenCan be slow nBus cycles must be constructed by laboriously shifting every bitnLoops can be extremely long(10,000 bits)nMethod of choice for processors in ASIC coresnLends itself to RISC processors because core logic tends to be simpler th