科技英语教案.ppt

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1、科技英语 Still waters run deep.流静水深流静水深,人静心深人静心深 Where there is life,there is hope。有生命必有希望。有生命必有希望FPGA Implementation of Modern Wireless Commuication SystemFPGA Implementation of Modern Wireless Commuication System题目：题目：现代无线通信系统的FPGA实现Abstract:OFDM is considered as an important constituent of modern wir

2、eless communication systems because of its capability to provide high data rates,highspectral efficiency and robustness against both inter-symbol and intra-symbol interference.摘要摘要：OFDM具有高数据传输速率、高频率利用率、强抗码间、内部码间干扰能力的特点，被认为是现代无线通信系统的重要组成部分。OFDM：(Orthogonal Frequency Division Multiplexing)即正交频分复用技术，是多

3、载波调制的一种。其主要思想是：将信道分成若干正交子信道，将高速数据信号转换成并行的低速子数据流，调制到在每个子信道上进行传输。正交信号可以通过在接收端采用相关技术来分开，这样可以减少子信道之间的相互干扰。每个子信道上的信号带宽小于信道的相关带宽，因此每个子信道上的可以看成平坦性衰落，从而可以消除符号间干扰。而且由于每个子信道的带宽仅仅是原信道带宽的一小部分，信道均衡变得相对容易。Abstract：OFDM inherently perform its operations in parallel fashion,so it is vital that any implem-entation s

4、hould execute OFDMs operation in p-arallel by default.This paper is focused on imp-lementing different OFDM modules on modern FPGA devices.摘要摘要：OFDM的工作方式为并行，因此任何实现方式须以并行方式执行。本文论述了不同的OFDM模块在FPGA上的实现。Keywords:OFDM,FPGA,Altera,DSP Builder,Cyclon devices关键字：关键字：OFDM,FPGA,Altera,DSP Builder，Cyclon device

5、s一些名词inter-symbol 码间intra-symbol 内部码间parallel fashion/mode 并行方式serial mode 串行方式Convolutional Encoder 卷积编码器Block interleaver 块分组交织器QAM Mapper 正交幅度调制映射simulation 仿真implemetation 实现Viterbi Decoder 维特比译码器 交织器通常是对输入的原始信息序列进行随机置换后从前向后读出。交织器的作用是：一、可以产生长码。二、使两个编码器的输入不相关，编码过程趋于独立。交织使编码产生随机度，使码随机化、均匀化，起着对码重量整

6、形的作用，直接影响码的性能。交织方式主要有规则交织，不规则交织和随机交织3种。通常规则交织即行写列读，效果不好。随机交织指交织格式是随机分配的，是理论上性能最好的交织方式，但是由于要将整个交织信息位置信息传送给译码器，降低了编码效率。实际应用中一般采用不规则交织，这是一种伪随机交织方式，对每一编码块采用固定的交织方式，但块与块之间交织器结构不一样。往往为了获得高的编码增益对交织器的长度提出要求。在无线移动通信系统对时延要求较高，因此采用交织长度为400左右的伪随机短交织器。Conclusion Different components of OFDM systen were using Alt

7、era DSP Builder Technology in the Simulink environ-ment.All the simulations were done successfully in this industry-standard MATLAB environment,and then the D-SP signal compiler was used for compilation,synthesis and design fitting.结论结论：OFDM系统的不同组件都可以使用Altera公司 DSP Builder技术进行仿真。首先，在Matlab环境下进行仿真，成功

8、实现后，再使用DSP信号编译器进行编译，综合和设计拟合。Conclusion After these steps all the modules were independently implemented on Altera Cyclone chips.Outputs were shown on the physical deivce and verified and compared with simulation(and litereature)results.结论：结论：经过这些步骤，将所有的模块独立在Altera公司的Cyclone芯片上运行。将输出显示在物理设备，经过验证，并且与仿

9、真结果进行比较。Conclusion In short Altera Cyclone chips can easily be used for implementation of different modules of OFDM system and of course the FPGA designs are flexble enough to b-e given priority over both ASIC and microcontroller-based design.结论：结论：总之，OFDM系统的不同模块可以在Altera公司的Cyclone芯片很容易的实现，并且与ASIC和基

10、于微控制器设计相比，FPGA还具有设计的灵活性，因此无线通信的FPGA实现具有非常现实的意义。Future work This piece of work can be extended in future by impl-ementing transmitter and receiver on separate chips and then sending and receving the data independently and fin-ally one can analyse different things like effect of channel and maximum ac

11、hievable data rates.If one succeeds in im-plementing transmitter and receiver separately,then re-sults can be compared with conventional implemetation techiqu-es and can investigate the difference.这项工作可以扩展到在不同的芯片上发射和接收，发送和接收数据独立，可以分析不同通道数的影响和可达到的最大数据速率。一旦这项研究成功，将结果与用传统方法得到的结果进行对比，比较两者不同。Ackonwledgem

12、entFPGA Based High Speed BCH Encoder for Wireless Communication ApplicationFPGA Based High Speed BCH Encoder for Wireless Communication Application题目：题目：基于高速BCH编码器的FPGA在无线通信中的应用 BCH码是一类重要的纠错码，它把信源待发的信息序列按固定的位一组划分成消息组,再将每一消息组独立变换成长为n(n)的二进制数字组,称为码字。如果消息组的数目为M(显然M2),由此所获得的M个码字的全体便称为码长为n、信息数目为M的分组码,记为n

13、，M。把消息组变换成码字的过程称为编码，其逆过程称为译码。Abstract This paper presents prototyping of a high speed and area efficient BCH encoder on an FPGA target device for wireless communication applications.FPGA implemetai-on is very fast,easy to modify and suitable for prototyping products.本文介绍了一种应用于无线通信技术的基于BCH编码器的FPGA器件。

14、FPGA具有快速实现、易于修改、适合原型器件的特点。Abstract BCH encoder is usually implemented with linear fe-edback shift register architecture.BCH codes can be de-fined by two parameters that are numbers of errors to be corrected and code size.The proposed BCH encoder h-as been developed and simulated using MATLAB along w

15、ith Xinlinx DSP Tools,synthesized with XST and imple-mented on Spartan 3E target FPGA device.BCH编码器通常应用于线性反馈移位寄存器。BCH码有两个参数，分别对误差进行修正和对代码尺寸数字定义。提及的BCH编码器已使用MATLAB和Xilinx公司的 DSP工具进行了仿真，与XST合成并应用于Spartan 3E FPGA器件上。Abstract The results show that proposed BCH encoder can opreate at a maximum frequency

16、of 249.8 MHZ by con-suming negligible resources of target device.结果表明，提出的BCH编码器在忽略其他资源的情况下，运行时可以达到的最大频率为249.8兆赫 Keywords:ARQ,BCH encoding,CRT,FEC,LFSR关键词关键词：自动重复请求，BCH编码器，阴极射线管,前向纠错，线性反馈移位寄存器Conclusion In this paper,high speed design of BCH encoder is proposed for wireless communication based system

17、s.The proposed design has shown an efficient realization of BCH encoder by using embedded LUTs of target FP-GA to provide high speed operation.The results have b-een verifided through Xilinx DSP Tool simulation and te-sting.在本文中，提出了将高速的BCH编码器用于无线通信系统。该设计通过使用FPGA器件嵌入LUTS成功实现BCH编码器。结果已经通过Xilinx DSP仿真和

18、测试工具进行了验证。Conclusion The proposed BCH Encoder has been implemented on Spartan 3E based xc3s500e target device using fully parallel LUT based mu-ltiplier less technique.The results show that proposed design can w-ork at an estimated fre-quency of 249.8MHz by using negligible res-ources of target FPGA to provide cost effective solution for wirele-ss communication systems.提出的BCH编码器已经在基于XC3S500E器件的Spar-tan 3E上采用完全并行LUT的乘数算法实现。结果表明，所提出的设计在249.8mhz频率下工作仅使用FPGA很少的资源，并且成本很低，对无线通信技术的发展具有可观的意义。Ackonwledgement谢谢大家！