半导体物理学半导体 (47).pdf

《半导体物理学半导体 (47).pdf》由会员分享，可在线阅读，更多相关《半导体物理学半导体 (47).pdf（13页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、The CMOS TechnologyCMOS operating principleCMOS circuit processCMOS inverter010203 CMOS(Complementary MOS):a pair of complementary p-channel and n-channel MOSFET.CMOS logic:most commonly used technique in IC design because of its low power loss and good noise suppression capability.N-channel and p-c

2、hannel enhancement mode MOSFETs are used in a CMOS inverter,which is the basis of CMOS digital logic circuits.The DC power dissipation in a digital circuit can be reduced to very low levels by using a complementary p-channel and n-channel pair.Due to low power loss requirements,only CMOS technology

3、is currently used in ULSI manufacturing.The CMOS Technology p channel and n channel MOSFET are both enhanced transistors.Gate are connected:input terminal Drain terminals are connected:output terminal.The source of the n-channel MOSFET is grounded to the substrate contact The source of the p-channel

4、 MOSFET is connected to the substrate to the power supply terminal(VDD).CMOS inverterStructureWhen the input voltage is low(Vin=0,VGSn=0VTn),the n channel MOSFET is closed.However,since|VGSp|VDD|VTp|(VGSpand VTpare negative),the p channel MOSFET is in the conduction state.The output terminal is char

5、ged to VDDvia the p channel MOSFET.When the input voltage is gradually increased so that the gate voltage is equal to VDD,since VGSn=VDDVTn,the n channel MOSFET will be conducted,while the p channel MOSFET will be closed because|VGSp|0|VTp|.Therefore,the output terminal will discharge through the n

6、channel MOSFET to zero potential.CMOS operating principle An important feature:When the output is in a logical steady state(Vout=0 or VDD),only one transistor is conducted,so the current flowing from the power supply to the ground is very small and is equivalent to the drain current when the device

7、is turned off.ABDC0DDVoutVDDVinVThe transmission curve of CMOS inverterLarge current flows only during the very short state time when two devices are temporarily conducting.Therefore,compared with other kinds of logic circuits such as n-channel MOSFET and bipolar,its steady-state power loss is very

8、low.CMOS operating principle p and n substrate regions:electrically isolation in an IC.The p-well process:a commonly used technique for CMOS circuits.The process:(1)a fairly low doped n-type Si:p-channel MOSFET;(2)A diffused p region,called a p well:n-channel MOSFET.In most cases,the p-type substrat

9、e doping level must be larger than the n-type substrate doping level to obtain the desired VT.The larger p doping can easily compensate the initial n doping to form the p well.CMOS circuit process(p-well process)FOX(Field oxide):a relatively thick oxide separating the devices.The FOX prevents either

10、 the n or p substrate from becoming inverted and helps maintain isolation between the two devices.Additional processing steps:e.g.providing connections so that the p-well and n-substrate can be electrically connected to the appropriate voltages.The n substrate must always be at a higher potential th

11、an the p well;therefore,this pn junction will always be reverse biased.CMOS structures:p wellCMOS circuit process(p-well process)Ion implantation:now being extensively used for VTcontrol,both the n-well CMOS process and twin-well CMOS process can be used.The n-well CMOS process:(1)an optimized p-typ

12、e substrate:n-channel MOSFETs.(having superior characteristics)(2)The n well is then added:p-channel devices are fabricated.The n-well doping can be controlled by ion implantation.CMOS circuit process(n-well process)CMOSstructures:n well The twin-well CMOS process,allows both the p-well and n-well r

13、egions to be optimally doped to control the VTand transconductance of each transistor.The twin-well process allows a higher packing densitybecause of self-aligned channel stops.CMOS circuit process(twin-well process)CMOS structures:twin wellOne major problem in CMOS circuits:latch-up.Latch-up:a high

14、-current,low-voltage condition that may occur in a four-layer pnpn structure.In the CMOS layout,p+source to n substrate to p well to n+source forms such a four-layer structure.Latch-up effectSimplified integrated circuit cross sectionCMOS inverter circuit The silicon-controlled rectifier action invo

15、lves the interaction of the parasitic pnp and npn bipolar transistors.The npn transistor corresponds to the vertical n+source to p-well to n-substrate structure and the pnp transistorcorresponds to the lateral p-well to n-substrate to p+source structure.The two-transistor equivalent circuit of the f

16、our-layered pnpn deviceThe splitting of the basic pnpn structureLatch-up effect Under certain conditions,avalanche breakdown may occur in the p-well to n substrate junction,driving both into saturation.This high-current,low-voltage conditionlatch-up,can sustain itself by positive feedback.The condit

17、ion can prevent the CMOS circuit from operating and can also cause permanent damage and burnout of the circuit.The two-transistor equivalent circuit of the four-layered pnpn deviceThe splitting of the basic pnpn structureUnder normal CMOS operation,both are cut off.Latch-up effect1.Latch-up can be p

18、revented if the product np is less than unity at all times,where n and p are the common-emitter current gains of the npn and pnp parasitic bipolar transistors,respectively.2.Preventing latch-up:(1)To kill the minority carrier lifetime.Minority carrier lifetime degradation can be accomplished by gold

19、 doping or neutron irradiation(introduces deep traps within the semiconductor).The deep traps increase the excess minority carrier recombination rate and reduce current gain.(2)Using proper circuit layout techniques.Decoupling two bipolar transistors,e.g.by using a different fabrication technology like the silicon-on-insulator technology.It allows the n-channel and the p-channel MOSFETs to be isolated from each other by an insulator.Latch-up effect