数字电子技术（Floyd第十版）ppt课件.ppt

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1、 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edDigital FundamentalsTenth EditionFloydChapter 9 2008 Pearson Education 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edA shift register is

2、an arrangement of flip-flops with important applications in storage and movement of data.Some basic data movements are illustrated here.SummaryBasic Shift Register OperationsData inData inData inData inData inData outData outData outData outData outSerial in/shift right/serial outSerial in/shift lef

3、t/serial outParallel in/serial outParallel in/parallel outSerial in/parallel outRotate rightRotate left 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummarySerial-in/Serial out Shift RegisterShift registers are available in IC form or can be

4、 constructed from discrete flip-flops as is shown here with a five-bit serial-in serial-out register.Each clock pulse will move an input bit to the next flip-flop.For example,a 1 is shown as it moves across.111111CLKCLKCLKCLKCLK 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedF

5、loyd,Digital Fundamentals,10th edSummaryA Basic ApplicationAn application of shift registers is conversion of serial data to parallel form.For example,assume the binary number 1011 is loaded sequentially,one bit at each clock pulse.CLKCLKCLKCLKAfter 4 clock pulses,the data is available at the parall

6、el output.2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryThe 74HC164A Shift Register The 74HC164A is a CMOS 8-bit serial in/parallel out shift register.VCC can be from+2.0 V to+6.0 V.One of the two serial data inputs may be used as an a

7、ctive HIGH enable to gate the other input.If no enable is needed,the other serial input can be connected to VCC.The 74HC164A has an active LOW asynchronous clear.Data is entered on the leading-edge of the clock.CLKQ0Q1Q2Q3CLRQ4Q5Q6Q7Serial inputsAB 2009 Pearson Education,Upper Saddle River,NJ 07458.

8、All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryWaveforms for the 74HC164ASample waveforms for the 74HC164A are shown.Notice that B acts as an active HIGH enable for the data on A as discussed.CLKQ0Q1Q2Q3CLRQ4Q5Q6Q7Serial inputsABOutputsClearClearAs with CMOS devices,unused inputs should

9、 always be connected to a logic level;unused outputs should be left open.2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryParallel in/Serial out Shift RegisterShift registers can be used to convert parallel data to serial form.A logic dia

10、gram for this type of register is shown:D0D1D2D3Q0Q1Q2Q3SHIFT/LOADCLKSerial data out 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryThe 74HC165 Shift Register The 74HC165 is a CMOS 8-bit parallel in/serial out shift register.The logic s

11、ymbol is shown:D0D1D2D3D4D5D6D7Q7Q7SH/LDCLKSERCLK INHThe clock(CLK)and clock inhibit(CLK INH)lines are connected to a common OR gate,so either of these inputs can be used as an active-LOW clock enable with the other as the clock input.Data is loaded asynchronously when SH/LD is LOW and moved through

12、 the register synchronously when SH/LD is HIGH and a rising clock pulse occurs.2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryThe 74HC165 Shift Register A Multisim simulation of the 74165A is shown.The word generator is used as a source

13、 for the pattern shown in the green probes.MSBPattern is loaded when J1 is LOWQ7 is labeled QH in Multisim 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryThe 74HC165 Shift Register Here the scope is opened and you can observe the patter

14、n.The MSB is HIGH and is on the Q7 output as soon as LOAD is LOW.LoadQ7ClkMSB 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryBidirectional Shift RegisterBidirectional shift registers can shift the data in either direction using a RIGHT/

15、LEFT input.The logic analyzer simulation shows a bidirectional shift register such as the one shown in Figure 9-19 of the text.Notice the HIGH level from the Serial data in is shifted at first from Q3 toward Q0.CLKRIGHT/LEFTSerial data inQ0Q1Q2Q3Shift right Shift left 2009 Pearson Education,Upper Sa

16、ddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryBidirectional Shift RegisterCLKRIGHT/LEFTSerial data inQ0Q1Q2Q3Shift right Shift leftHow will the pattern change if the RIGHT/LEFT control signal is inverted?See displayShift right Shift left 2009 Pearson Education,Upper

17、 Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryUniversal Shift RegisterA universal shift register has both serial and parallel input and output capability.The 74HC194 is an example of a 4-bit bidirectional universal shift register.D0D1D2D3CLKSL SERQ0Q1Q2Q3SR SERS1

18、S0CLRSample waveforms are on the following slide 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryUniversal Shift Register 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryShif

19、t Register CountersShift registers can form useful counters by recirculating a pattern of 0s and 1s.Two important shift register counters are the Johnson counter and the ring counter.The Johnson counter can be made with a series of D flip-flops or with a series of J-K flip flops.Here Q3 and Q3 are f

20、ed back to the J and K inputs with a“twist”.2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryJohnson Counter“twist”Redrawing the same Johnson counter(without the clock shown)illustrates why it is sometimes called as a“twisted-ring”counter

21、.2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryJohnson CounterThe Johnson counter is useful when you need a sequence that changes by only one bit at a time but it has a limited number of states(2n,where n=number of stages).The first fi

22、ve counts for a 4-bit Johnson counter that is initially cleared are:CLK Q0 Q1 Q2 Q30 0 0 01 0 0 01 1 0 01 1 1 01 1 1 10 1 1 1 0 0 1 1 0 0 0 101234567What are the remaining 3 states?2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryRing Cou

23、nterThe ring counter can also be implemented with either D flip-flops or J-K flip-flops.Here is a 4-bit ring counter constructed from a series of D flip-flops.Notice the feedback.Like the Johnson counter,it can also be implemented with J-K flip flops.2009 Pearson Education,Upper Saddle River,NJ 0745

24、8.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryRing CounterRedrawing the Ring counter(without the clock shown)shows why it is a“ring”.The disadvantage to this counter is that it must be preloaded with the desired pattern(usually a single 0 or 1)and it has even fewer states than a John

25、son counter(n,where n=number of flip-flops.On the other hand,it has the advantage of being self-decoding with a unique output for each state.2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryRing CounterA common pattern for a ring counter

26、is to load it with a single 1 or a single 0.The waveforms shown here are for an 8-bit ring counter with a single 1.2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryShift Register ApplicationsShift registers can be used to delay a digital

27、signal by a predetermined amount.An 8-bit serial in/serial out shift register has a 40 MHz clock.What is the total delay through the register?The delay for each clock is 1/40 MHz=25 nsThe total delay is 8 x 25 ns=200 ns25 ns=200 ns 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights Reserv

28、edFloyd,Digital Fundamentals,10th edSummaryShift Register ApplicationsA UART(Universal Asynchronous Receiver Transmitter)is a serial-to-parallel converter and a parallel to serial converter.UARTs are commonly used in small systems where one device must communicate with another.Parallel data is conve

29、rted to asynchronous serial form and transmitted.The serial data format is:StartBit(0)Stop Bits(1)Data busSerial data inSerial data outCLKCLK 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edSummaryKeyboard EncoderThe keyboard encoder is an exam

30、ple of where a ring counter is used in a small system to encode a key press.Two 74HC195 shift registers are connected as an 8-bit ring counter preloaded with a single 0.As the 0 circulate in the ring counter,it“scans”the keyboard looking for any row that has a key closure.When one is found,a corresp

31、onding column line is connected to that row line.The combination of the unique column and row lines identifies the key.The schematic is shown on the following slide 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th ed 2008 Pearson Education 2009 Pe

32、arson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edKey Terms Register StageShiftLoadBidirectionalOne or more flip-flops used to store and shift data.One storage element in a register.To move binary data from stage to stage within a shift register or othe

33、r storage device or to move binary data into or out of the device.To enter data in a shift register.Having two directions.In a bidirectional shift register,the stored data can be shifted right or left.2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10

34、th ed1.The shift register that would be used to delay serial data by 4 clock periods is a.c.b.d.2008 Pearson Education 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th ed 2008 Pearson Education2.The circuit shown is aa.serial-in/serial-out shift r

35、egister b.serial-in/parallel-out shift registerc.parallel-in/serial-out shift registerd.parallel-in/parallel-out shift register 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th ed3.If the SHIFT/LOAD line is HIGH,dataa.is loaded from D0,D1,D2 and D

36、3 immediatelyb.is loaded from D0,D1,D2 and D3 on the next CLKc.shifted from left to right on the next CLKd.shifted from right to left on the next CLK 2008 Pearson Education 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th ed 2008 Pearson Education

37、4.A 4-bit parallel-in/parallel-out shift register will store data fora.1 clock periodb.2 clock periods c.3 clock periodsd.4 clock periods 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th ed5.The 74HC164(shown)has two serial inputs.If data is place

38、d on the A input,the B input a.could serve as an active LOW enableb.could serve as an active HIGH enablec.should be connected to groundd.should be left open 2008 Pearson EducationCLKQ0Q1Q2Q3CLRQ4Q5Q6Q7Serial inputsAB 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital

39、 Fundamentals,10th ed6.An advantage of a ring counter over a Johnson counter is that the ring counter a.has more possible states for a given number of flip-flopsb.is cleared after each cyclec.allows only one bit to change at a timed.is self-decoding 2009 Pearson Education,Upper Saddle River,NJ 07458

40、.All Rights ReservedFloyd,Digital Fundamentals,10th ed7.A possible sequence for a 4-bit ring counter isa.1111,1110,1101 b.0000,0001,0010 c.0001,0011,0111 d.1000,0100,0010 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th ed8.The circuit shown is aa

41、.serial-in/parallel-out shift registerb.serial-in/serial-out shift registerc.ring counterd.Johnson counter 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th ed9.Assume serial data is applied to the 8-bit shift register shown.The clock frequency is

42、20 MHz.The first data bit will show up at the output in a.50 nsb.200 nsc.400 nsd.800 ns 2008 Pearson Education 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th ed10.For transmission,data from a UART is sent ina.asynchronous serial formb.synchronous parallel formc.can be either of the aboved.none of the above 2008 Pearson Education 2009 Pearson Education,Upper Saddle River,NJ 07458.All Rights ReservedFloyd,Digital Fundamentals,10th edAnswers:1.a2.c3.c4.a5.b6.d7.d8.d9.c10.a