EDA技术与应用讲义第2章EDA设计流程及其工具.ppt

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1、第第2章章 EDA设计流程及其工具设计流程及其工具 课程讲义课程讲义合肥工业大学 彭良清本章内容1.EDA设计的一般步骤2.常用EDA工具软件3.使用MAX+PLUSII软件设计过程4.使用QuartusII软件设计过程5.硬件设计和软件设计的时间协调6.设计的几个问题EDA设计的一般步骤1.电路的模块划分2.设计输入3.器件和引脚指配4.编译与排错5.功能仿真和时序仿真6.编程与配置，设计代码的芯片运行电路的模块划分v人工人工 根据电路功能进行模块划分模块划分v合理的模块划分关系到1.电路的性能2.实现的难易程度v根据模块划分和系统功能确定确定：PLD芯片型号芯片型号模块划分后，就可以进行模

2、块划分后，就可以进行 具体设计具体设计 了了设计输入一般EDA软件允许3种设计输入：1.HDL语言2.电路图3.波形输入何为？器件和引脚指配v器件指配F为设计输入选择合适的PLD器件型号v何谓引脚指配F将设计代码（图形）中的端口（端口（PORT）和PLD芯片的引脚芯片的引脚 （PIN）对应起来的.v指配文件FMAX+PLUSII：“*.acf”FQuartusII：“*.qsf”器件和引脚指配的方法方法有2种1.在软件的菜单界面中指配2.修改指配文件（是文本文件）菜单界面中指配修改指配文件vCHIPio_2d_lockvBEGINv|iVD:INPUT_PIN=7;v|iHD:INPUT_PI

3、N=8;v|iDENA:INPUT_PIN=6;v|iCLK:INPUT_PIN=211;v|oCLK:OUTPUT_PIN=237;v|oVD:OUTPUT_PIN=234;v|oHD:OUTPUT_PIN=233;v|oDENA:OUTPUT_PIN=235;v.vDEVICE=EPF10K30AQC240-2;vEND;v.编译与排错编译过程有2种，作用分别为：1.语法编译：只是综合并输出网表F编译设计文件，综合产生门级代码F编译器只运行到综合这步就停止了F编译器只产生估算的延时数值2.完全的编译：包括编译，网表输出，综合，配置器件F编译器除了完成以上的步骤，还要将设计配置到ALTERA

4、的器件中去F编译器根据器件特性产生真正的延时时间和给器件的配置文件功能仿真和时序仿真v仿真的概念：在设计代码下载到芯片前，在EDA软件中对设计的输出进行波形仿真。v常用的2种仿真模式1.功能仿真对设计的逻辑功能进行仿真2.时序仿真对设计的逻辑功能和信号的时间延时进行仿真。v仿真前还要做的工作输入信号的建立Quartus II软件中软件中关于仿真的原文关于仿真的原文2种仿真文件1.矢量波形文件：vaVectorWaveformFile(.vwf)2.文本矢量文件vatext-basedVectorFile(.vec),编程与配置最后，最后，如果仿真如果仿真 也正确也正确 的话，的话，那我们就可以

5、那我们就可以 将设计代码将设计代码 配置或者编程配置或者编程 到到 芯片芯片 中了中了v编程的文件类型对于CPLD或者EPC2，ECS1等配置芯片，编程文件扩展名为：“*.POF“v配置的文件类型对于FPGA芯片，配置文件扩展名为：“*.SOF“硬件设计和软件设计的时间协调1.软件模块划分，器件的初步信号确定（主要是根据需要的I/O引脚的数量）2.软件设计，硬件外围电路设计和器件选择3.软件仿真4.仿真完成后，器件信号的重新审核，进行硬件电路图设计5.综合调试6.完成设计的几个问题v如何组织多个设计文件的系统？，项目的概念。v时钟系统如何设计？v电路的设计功耗v高速信号的软件和硬件设计The

6、end.以下内容以下内容为为正文的引用，正文的引用，可不阅读。可不阅读。常用EDA工具软件vEDA软件方面，大体可以分为两类：1.PLD器件厂商提供的EDA工具。较著名的如：I.Altera公司的Max+plusII和QuartusII、II.Xilinx公司的FoundationSeries、III.Latice-Vantis公司的ispEXERTSystem。2.第三方专业软件公司提供的EDA工具。常用的有：I.Synopsys公司的FPGACompilerII、II.ExemplarLogic公司的LeonardoSpectrum、III.Synplicity公司的Synplify。v第

7、三方工具软件是对CPLD/FPGA生产厂家开发软件的补充和优化，如通常认为Max+plusII和QuartusII对VHDL/VerilogHDL逻辑综合能力不强，如果采用专用的HDL工具进行逻辑综合，会有效地提高综合质量。ALTERA 公司的公司的EDA合作伙伴合作伙伴硬件描述语言：起源v是电子电路的文本描述。v最早的发明者：美国国防部，美国国防部，VHDL,1983v大浪淘沙，为大者二：VHDL 和 Verilog HDLv其他的小兄弟：ABEL、AHDL、System Verilog、System C。一个D触发器的VHDL代码例子1.-VHDLcodeposition:p83_ex4_

8、11_DFF12.-3.-LIBARYIEEE;4.-USEIEEE.STD_LOGIC_1164.ALL;5.ENTITYDFF1IS6.PORT(CLK:INBIT;7.D:INBIT;8.Q:OUTBIT9.);10.ENDENTITYDFF1;11.ARCHITECTUREbhvOFDFF1IS12.BEGIN13.PROCESS(CLK)14.BEGIN15.IFCLKEVENTAND(CLK=1)AND(CLKLAST_VALUE=0)THEN16.-严格的CLK信号上升沿定义17.QCompiler Netlist Extractor（编译器网表提取器）（编译器网表提取器）vTh

9、eCompilermodulethatconvertseachdesignfileinaproject(oreachcellofanEDIFInputFile)intoaseparatebinaryCNF.Thefilename(s)oftheCNF(s)arebasedontheprojectname.ExamplevTheCompilerNetlistExtractoralsocreatesasingleHIFthatdocumentsthehierarchicalconnectionsbetweendesignfiles.vThismodulecontainsabuilt-inEDIFN

10、etlistReader,VerilogNetlistReader,VHDLNetlistReader,andconvertersthattranslateADFsandSMFsforusewithMAX+PLUSII.vDuringnetlistextraction,thismodulecheckseachdesignfileforproblemssuchasduplicatenodenames,missinginputsandoutputs,andoutputsthataretiedtogether.v返回DatabaseBuilder(数据库构建器):vThe Compiler modu

11、le that builds a single,fully flattened project database that integrates all the design files in a project hierarchy.vThe Database Builder uses the HIF to link the CNFs that describe the project.Based on the HIF data,the Database Builder copies each CNF into the project database.Each CNF is inserted

12、 into the database as many times as it is used within the original hierarchical project.The database thus preserves the electrical connectivity of the project.vThe Compiler uses this database for the remainder of project processing.Each subsequent Compiler module updates the database until it contai

13、ns the fully optimized project.In the beginning,the database contains only the original netlists;at the end,it contains a fully minimized,fitted project,which the Assembler uses to create one or more files for device programming.vAs it creates the database,the Database Builder examines the logical c

14、ompleteness and consistency of the project,and checks for boundary connectivity and syntactical errors(e.g.,a node without a source or destination).Most errors are detected and can be easily corrected at this stage of project processing.v返回LogicSynthesizervTheCompilermodulethatsynthesizesthelogicina

15、projectsdesignfiles.vUsingthedatabasecreatedbytheDatabaseBuilder,theLogicSynthesizercalculatesBooleanequationsforeachinputtoaprimitiveandminimizesthelogicaccordingtoyourspecifications.vForprojectsthatuseJKorSRflipflops,theLogicSynthesizercheckseachcasetodeterminewhetheraDorTflipflopwillimplementthep

16、rojectmoreefficiently.DorTflipflopsaresubstitutedwhereappropriate,andtheresultingequationsareminimizedaccordingly.vTheLogicSynthesizeralsosynthesizesequationsforflipflopstoimplementstateregistersofstatemachines.AnequationforeachstatebitisoptimallyimplementedwitheitheraDorTflipflop.Ifnostatebitassign

17、mentshavebeenmade,orifanincompletesetofstatebitassignmentshasbeencreated,theLogicSynthesizerautomaticallycreatesasetofstatebitstoencodethestatemachine.Theseencodingsarechosentominimizetheresourcesused.v返回Fitter（适配器）vTheCompilermodulethatfitsthelogicofaprojectintooneormoredevices.vUsingthedatabaseupd

18、atedbythePartitioner,theFittermatchesthelogicrequirementsoftheprojectwiththeavailableresourcesofoneormoredevices.Itassignseachlogicfunctiontothebestlogiccelllocationandselectsappropriateinterconnectionpathsandpinassignments.vTheFitterattemptstomatchanyresourceassignmentsmadefortheprojectwiththeresou

19、rcesonthedevice.Ifitcannotfindafit,theFitterallowsyoutooverridesomeorallofyourassignmentsorterminatecompilation.vTheFittermodulegeneratesaFitFilethatdocumentspin,buriedlogiccell,chip,clique,anddeviceassignmentsmadebytheFittermoduleinthelastsuccessfulcompilation.Eachtimetheprojectcompilessuccessfully

20、,theFitFileisoverwritten.Youcanback-annotatetheassignmentsinthefiletopreservetheminfuturecompilations.v返回TimingSNFExtractor(时序SNF文件提取器)vTheCompilermodulethatcreatesatimingSNFcontainingthelogicandtiminginformationrequiredfortimingsimulation,delayprediction,andtiminganalysis.vTheTimingSNFExtractoristu

21、rnedonwiththeTimingSNFExtractorcommand(Processingmenu).ItisalsoturnedonautomaticallywhenyouturnontheEDIFNetlistWriter,VerilogNetlistWriter,orVHDLNetlistWritercommand(Interfacesmenu).TheTimingSNFExtractorcannotbeturnedonatthesametimeastheFunctionalSNFExtractorortheLinkedSNFExtractor.vAtimingSNFdescri

22、besthefullyoptimizedcircuitafteralllogicsynthesisandfittinghavebeencompleted.Regardlessofwhetheraprojectispartitionedintomultipledevices,thetimingSNFdescribesaprojectasawhole.Therefore,timingsimulationandtiminganalysis(includingdelayprediction)areavailableonlyfortheprojectasawhole.Neithertimingsimul

23、ationnorfunctionaltestingisavailableforindividualdevicesinamulti-deviceproject.Functionaltestingisavailableonlyforasingle-deviceproject.v返回Assembler（汇编器）vTheCompilermodulethatcreatesoneormoreprogrammingfilesforprogrammingorconfiguringthedevice(s)foraproject.vTheAssemblermodulecompletesprojectprocess

24、ingbyconvertingtheFittersdevice,logiccell,andpinassignmentsintoaprogrammingimageforthedevice(s),intheformofoneormorePOFs,SOFs,HexFiles,TTFs,JamFiles,JBCFiles,and/orJEDECFiles.POFsandJEDECFilesarealwaysgenerated;SOFs,HexFiles,andTTFsarealwaysgeneratediftheprojectusesACEX1K,FLEX6000,FLEX8000orFLEX10Kd

25、evices;andJamFilesandJBCFilesarealwaysgeneratedforMAX9000,MAX7000B,MAX7000AEorMAX3000Aprojects.IfyouturnontheEnableJTAGSupportoptionintheClassic&MAXGlobalProjectDeviceOptionsdialogbox(Assignmenu)ortheClassic&MAXIndividualDeviceOptionsdialogbox,theAssemblerwillalsogenerateJamFilesandJBCFilesforMAX700

26、0AorMAX7000Sprojects.Aftercompilation,youcanalsouseSOFstocreatedifferenttypesoffilesforconfiguringFLEX6000,FLEX8000andFLEX10KdeviceswithConvertSRAMObjectFiles(Filemenu).vTheprogrammingfilescanthenbeprocessedbytheMAX+PLUSIIProgrammerandtheMPUorAPUhardwaretoproduceworkingdevices.Severalotherprogrammin

27、ghardwaremanufacturersalsoprovideprogrammingsupportforAlteradevices.v返回SimulationModevFunctionalSimulatesthebehaviorofflattenednetlistsextractedfromthedesignfiles.YoucanuseTclcommandsandscriptstocontrolsimulationandtoprovidevectorstimuli.YoucanalsoprovidevectorstimuliinaVectorWaveformFile(.vwf)orate

28、xt-basedVectorFile(.vec),althoughtheSimulatorusesonlythesequenceoflogiclevelchanges,andnottheirtiming,fromthevectorstimuli.Thistypeofsimulationalsoallowsyoutochecksimulationcoverage(theratioofoutputportsactuallytogglingbetween1and0duringsimulation,comparedtothetotalnumberofoutputportspresentinthenet

29、list).vTimingUsesafullycompilednetlistthatincludesestimatedoractualtiminginformation.YoucanuseTclcommandsandscriptstocontrolsimulationandtoprovidevectorstimuli.YoucanalsoprovidevectorstimuliinaVectorWaveformFile(.vwf)oratext-basedVectorFile(.vec).Thistypeofsimulationalsoallowsyoutochecksetupandholdt

30、imes,detectglitches,andchecksimulationcoverage(theratioofoutputportsactuallytogglingbetween1and0duringsimulation,comparedtothetotalnumberofoutputportspresentinthenetlist).vTiming using Fast Timing ModelPerformsatimingsimulationusingtheFastTimingModeltosimulatefastestpossibletimingconditionswiththefastestdevicespeedgrade