【精品】SoC设计方法与实现第十四章 IO环设计1精品ppt课件.ppt

《【精品】SoC设计方法与实现第十四章 IO环设计1精品ppt课件.ppt》由会员分享，可在线阅读，更多相关《【精品】SoC设计方法与实现第十四章 IO环设计1精品ppt课件.ppt（50页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、SoC设计方法与实现第十四章 IO环设计1 OutlinesBasic structure of I/O cellsNoise Cancellation ESD Protection SchemeI/O ring designPackage Selection OutlinesBasic structure of I/O cellsNoise Cancellation ESD Protection SchemeI/O ring designPackage SelectionPerformance with Die,Package,Board Three main killers of perf

2、ormancenPower supply noisenReference clock noisenSignal integrityThese challenges are relevant at the die,package,board and system levelThese challenges have existed at lower speeds but dramatically increase in high speedsI/O Cell I/O Cell Connect Core to Package Basic Structure of I/O cell Cont.Ana

3、log Input Cell:nESD protection without input resisterPower(VDD/VSS):nBig ESD protection cell for the I/O ring.Other cells:nFiller cell:provide connection for the power/ground ringnESD protection CellnDecoupling cellI/O Layout Bonding padI/O filler cellAs standard cellnHeightnPower linesnESDnLatch-up

4、 OutlinesBasic structure of I/O cellsNoise Cancellation ESD Protection SchemeI/O RingPackage SelectionNoise problem at High Speed I/OQ:Can simply increase driver size to meet high speed requirement?A:No!Problems when output signal at high speednRingingnBouncenEMI Noises Caused by Switching Activity

5、on Output RingingRinging:Oscillation on the signals at the switching pinsBounceEMI:Electromagnetic InterferenceEMI radiation is caused by High-frequency current but not by voltage perturbation.EMI cont.It is extremely dangerous for a wireless system.The Ultimate noise source is in the chip.Controlli

6、ng EMI at the chip level is becoming more critical.nSpecial design in I/O cell and I/O ring Noise Control I/O cellInput with noise immunity circuitOutput with slew rate control ncontrolling Ringing,Bounce and EMI Input Noise ImmunitySchmitt Trigger circuit is commonly used to increase noise immunity

7、 for“low speed”inputDrawback:large delay on the input signal.Commonly used for slow serial modules,e.g.I2C,SPIOutput Noise Control CircuitSlew rate controlnRinging cancellationnBounce reductionnEMI controlRinging Cancellation and Bounce ReductionExample circuit:Ringing Cancellation cont.Electromagne

8、tic Interference ControlEMI radiation is caused by High-frequency current(I)not by voltage(V)perturbation.But the slew rate of the signal,dV/dt,reflect the high-frequency current.Controlling Signal Parameters,Rise and Fall times,to reduce high frequency harmonics of signals and controls spectrum den

9、sity:Bounce ReductionDesign bounce detect and cancellation circuitn See the indication in Ringing CancellationReduce the number of I/Os which shares one pair of suppliesn More supplies for fast I/Os;less supplies for slow I/Os.Arrange the pin order to avoid switching at the same timen Example:put th

10、e I/O cells for address signal and data signal alternatively as they will not switching at the same time.Separate power domainsn Separate the power domain according to pad functions.Analog bank,fast digital bank,slow digital bank.Add Decoupling capacitors between I/O cellsn add decoupling cap on unu

11、sed empty space OutlinesBasic structure of I/O cellsNoise Cancellation ESD Protection SchemeI/O RingPackage SelectionElectro Static Discharge(ESD)Protection IC was damaged due to Electrical OverstressESD Test StandardStandard:JEDEC ESD standardnHuman Body Model(HBM)nMachine Model(MM)nCharge Device M

12、odel(CDM)Basic ESD requirement for productsHBMMMCDMPerformance2000V200V1000VOK10000V1000V2000VSupperESD Protection Reference:JAMES E.VINSON AND JUIN J.LIOU,SENIOR MEMBER,IEEE,Electrostatic Discharge in Semiconductor Devices:An Overview,Electrostatic Discharge in Semiconductor Devices:Protection Tech

13、niques,IEEE,1998.ESD Test Model Human Body Model (HBM)nApply a large voltageHBM test:Schematic and currentESD Test Model-contMachine Model(MM)nExample:test machine handler Apply big currentMM test:Schematic and currentESD Test Model-contCharge Device Model(CDM)nCharge accumulated inside of ICCDM is

14、the most dangerous case to damager the ICESD Test CasesI/O to power pinsESD Test Cases cont.Supply pinsESD Test Cases-contIO pin-to-pin ESD testESD Protection CircuitConcept:provide ESD paths(short-circuit path)in order to prevent the ESD current into internal circuitESD Protection SchemenInput prot

15、ectionnOutput protectionnVDD to VSSnESD Protection NetworkGlobal ESD Protection Global ESD protectionInput ESD Protection Circuit Two commonly used ESD protection circuitsOutput ESD Protection Circuit Two commonly used ESD protection circuits ESD Protection NetworkVDD to VSS ESD pathnESD voltage acr

16、oss VDD and VSS can be quickly discharged through the short-circuit path of turn-on NMOSEDS cell or P/G cellESD Protection Network cont.Provide ESD protection path between different power/ground levels OutlinesBasic structure of I/O cellsNoise Cancellation ESD Protection SchemeI/O ringPackage Select

17、ionI/O Ring ConnectionMake connection to power and ground linesMake a global ESD protectDesign considerations:nDie size impact nBounding abilitynESD protectionnNoise immunity Die Size Pad-limited vs.core-limitedDie Size cont.IO Cells with Fillers in In-line BondingnFor core-limitedAbutted IO Cells i

18、n Staggered Bonding nFor pad-limitedBonding CapabilityPackage Design Rule Example:Wire bond design rulePerformance ImprovementESD protectionnAdd more VDD/VSS or ESD protection cells on the empty spaceNoise Immunity nProper driver size:do not exceed the speed requirement nAdd decoupling cap in the em

19、pty spaceDecoupling cap may cause extra leakage power at 90nm process and belowDouble Bonding For low-pin-count package,double bonding for power and ground pins will prevent Electromigration,as well as reduce wiring inductanceImprove Noise ImmunitySeparate Power Domains on I/O RingSeparate Power DomainPower cut cell with/without ESD protectionPower Cut Cell with ESD Power Cut Cell with ESDSoC设计方法与实现设计方法与实现郭炜郭炜 郭筝郭筝 谢憬谢憬Thank you