【精品】vhdl双语教学第3章（可编辑.ppt

《【精品】vhdl双语教学第3章（可编辑.ppt》由会员分享，可在线阅读，更多相关《【精品】vhdl双语教学第3章（可编辑.ppt（90页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、VHDL双语教学第3章2023/2/2【可编辑】Agendan nOverviewnEntitynArchitecturenLibrary&UsenPackagenConfigurationBasic Language Frameworklibraryieee;useieee.std_logic_1164.all;-entityXYZisport(A,B,C:instd_logic;-CommentsF:outstd_logic);endXYZ;-architectureXYZ_archofXYZisbeginF=(AandB)or(BandC)or(CandA);endXYZ_arch;In

2、cludeIncludeEntityEntityArchitectureArchitectureAgendanOverviewn nEntityEntityn nKeywordsKeywordsnPortnGenericnArchitecturenLibrary&UsenPackagenConfigurationEntitylibraryieee;useieee.std_logic_1164.all;-entityentityXYZisisport(A,B,C:instd_logic;F:outstd_logic);endendXYZ;-architectureXYZ_archofXYZisb

3、eginF=(AandB)or(BandC)or(CandA);endXYZ_arch;IncludeIncludeEntityEntityArchitectureArchitectureEntity Examples(Adder)entity Full_Adder is port(X,Y,Cin:in Bit;Cout,Sum:out Bit);end entity Full_Adder;XYCinSumCoutEntity Examples(n-input AND)entity ANDN is generic(wid:integer:=2);port (X :in bit_vector(w

4、id-1 downto 0);F :out bit );end;Entity Example(Empty Entity)entity Test_Bench isend entity Test_Bench ;Test_BenchSignal GeneratorTest TargetAgendanOverviewn nEntityEntitynKeywordsn nPortPortnGenericnArchitecturenLibrary&UsenPackagenConfigurationEntity Definition(Ports)entityentity entity_name entity

5、_name is is Generics;Ports;Ports;Other Declarative Parts;Statements;endend entity entity_nameentity_name ;Port Example(ANDN)entity ANDN is generic(wid:integer:=2);port (X :in bit_vector(wid-1 downto 0);F :out bit );end;Port Examples(ROM)entity ROM is port(D0 :out bit;D1 :out bit;D2 :out bit;D3 :out

6、bit;D4,D5,D6,D7 :out bit;A :in bit_vector(7 down to 0);end ROM;ROMA0A1A2A3A4A5A6A7D0D1D2D3D4D5D6D7Port Examples(Adder)entity Full_Adder is port(X,Y,Cin:in Bit;Cout,Sum:out Bit);end entity Full_Adder;XYCinSumCoutPort Examples(n-input AND)entity ANDN is generic(wid:integer:=2);port (X :in bit_vector(w

7、id-1 downto 0);F :out bit );end;Port DefinitionPort(Port_Name,Port_Name:Dir Type:=Default_Val;Port_Name,Port_Name:Dir Type:=Default_Val;.Port_Name,Port_Name:Dir Type:=Default_Val;);Each Parts of Port portport (A0,A1 :in std_logic;A2 :in std_logic :=1;F0 :buffer std_logic;F1 :out std_logic;F2 :inout

8、std_logic ););Port Name Dir Type Default ValueType of“Dir”nInnOutnInoutnBuffernLinkageSignal DirectionOther ICOther ICDir Example portport(A0,A1:in std_logic;A2 :in std_logic:=1;F0 :buffer std_logic;F1 :out std_logic;F2 :inout std_logic););Use of Dirlibraryieee;useieee.std_logic_1164.all;-entityABCi

9、sport(A0,A1,A2A0,A1,A2:ininstd_logic;F0F0:bufferbufferstd_logic;F1F1:outoutstd_logic;F2F2:inoutinoutstd_logic);endABC;-architectureABC_archofABCisbeginprocess(A0A0)beginifrising_edge(A0A0)thenF0F0=notF0F0;F1F1=F2F2;endif;endprocess;F2F2=A1A1whenA2A2=1ELSEZ;endABC_arch;Type portport (A0,A1 :in std_lo

10、gic;A2 :in std_logic :=1;F0 :buffer std_logic;F1 :out std_logic;F2 :inout std_logic ););Port Name Dir Type Default ValueTypical Port TypenBitnBit_vectornStd_logicnStd_logic_vectorBitn1n0Bit_vectorport(X :in bit_vector(3 downto 0);F :out bit);X0X1X2X3FPort(X0:in bit;X1:in bit;X2:in bit;X3:in bit;F :o

11、ut bit);Port(X0,X1,X2,X3:in bit;F :out bit);Std_logicnU,-UninitializednX,-Forcing Unknownn0,-Forcing 0n1,-Forcing 1nZ,-High Impedance nW,-Weak UnknownnL,-Weak 0 nH,-Weak 1 n-Dont care?Resolution Function Of Std_logicU X 01 Z W L H-U U U U U U U U U UX U X X X X X X X X0 U X 0 X 0000 X1 U X X 11111 X

12、Z U X 01 Z W L H XW U X 01 W W W W XL U X 01 L W L W XH U X 01 H W W H X-U X X X X X X X X10?Std_logic_vectorport(X :in std_logic_vector(3 downto 0);F :out std_logic);X0X1X2X3FAgendanOverviewn nEntityEntitynKeywordsnPortn nGenericGenericnArchitecturenLibrary&UsenPackagenConfigurationEntity Definitio

13、n(Generics)entityentity entity_name entity_name is is Generics;Generics;Ports;Other Declarative Parts;Statements;endend entity entity_nameentity_name ;An AND Gate With Unknown Inputsentity ANDN is generic(wid:integer:=2);port (X :in bit_vector(wid-1 downto 0);F :out bit );end ANDN;Generic Definition

14、generic(Name,Name:DataType:=DefaultValue;Name,Name:DataType:=DefaultValue;.Name,Name:DataType:=DefaultValue);Generic Example(1)entity abcd is generic(p_a:integer:=2;p_b:integer:=7 );port(A :out bit_vector(0 to p_a-1);F :in bit );end;Use of the Generic(ANDN.vhd)libraryieee;useieee.std_logic_1164.all;

15、-entityentityANDNANDNisgenericgeneric(widwid:integer:=2);port(X:inbit_vector(widwid-1downto0);F:outbit);endendANDNANDN;-architectureANDN_archofANDNANDNisbeginprocess(X)variabletmp:bit;begintmp:=1;foriinwidwid-1downto0looptmp:=tmpandX(i);endloop;F=tmp;endprocess;endANDN_arch;Use of the Generic(My_pac

16、kage.vhd)libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;-packagemy_packageiscomponentcomponentANDNANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);endendcomponent;endmy_package;libraryieee;useieee.std_logic_1164.all;libraryw

17、ork;usework.my_package.all;-entitySEEisport(A:inbit_vector(3downto0);B:inbit_vector(1downto0);F1,F2:outbit);endSEE;-architectureSEE_archofSEEisbeginU1:ANDNANDNgeneric map(4)generic map(4)portmap(A,F1);U2:ANDNANDNportmap(B,F2);endSEE_arch;Use of the Generic(see.vhd)U1A(0)A(1)A(2)A(3)F1U2B(1)B(3)F2Age

18、ndanOverviewnEntityn nArchitectureArchitecturen nKeywordsKeywordsnBlocknProcessnSubprogramnFunctionnProcedurenLibrary&UsenPackagenConfigurationArchitecturelibraryieee;useieee.std_logic_1164.all;-entityXYZisport(A,B,C:instd_logic;F:outstd_logic);endXYZ;-architectureXYZ_archofXYZisbeginF=(AandB)or(Ban

19、dC)or(CandA);endXYZ_arch;IncludeIncludeEntityEntityArchitectureArchitectureArchitecture Definitionarchitecture arch_name of entity_name is architecture_declarative_partbegin architecture_statement_partend architecture arch_name ;Architecture Example(ABC.vhd)libraryieee;useieee.std_logic_1164.all;-en

20、tityABCisport(A0,A1,A2:instd_logic;F0:bufferstd_logic;F1:outstd_logic;F2:inoutstd_logic);endABC;-architecturearchitectureABC_archofofABCisisbeginbeginprocess(A0)beginifrising_edge(A0)thenF0=notF0;F1=F2;endif;endprocess;F2=A1whenA2=1ELSEZ;endABC_arch;Architecture Example(ANDN.vhd)libraryieee;useieee.

21、std_logic_1164.all;-entityANDNisgeneric(wid:integer:=2);port(X:inbit_vector(wid-1downto0);F:outbit);endANDN;-architecturearchitectureANDN_archANDN_archofofANDNisisbeginbeginprocess(X)variabletmp:bit;begintmp:=1;foriinwid-1downto0looptmp:=tmpandX(i);endloop;F=tmp;endprocess;endendANDN_archANDN_arch;U

22、se of the Generic(see.vhd)libraryieee;useieee.std_logic_1164.all;librarywork;usework.my_package.all;-entitySEEisport(A:inbit_vector(3downto0);B:inbit_vector(1downto0);F1,F2:outbit);endSEE;-architecturearchitectureSEE_archofofSEEisisbeginbeginU1:ANDNgenericmap(4)portmap(A,F1);U2:ANDNportmap(B,F2);end

23、endSEE_arch;U1A(0)A(1)A(2)A(3)F1U2B(1)B(3)F2AgendanOverviewnEntityn nArchitectureArchitecturenKeywordsn nBlockBlocknProcessnSubprogramnFunctionnProcedurenLibrary&UsenPackage nConfigurationInside ArchitecturenHow to maintain large architecture?nHow to modulate the architecture code?nSeparate the arch

24、itecture in to several partsnHow to separate the architecture?nVHDL language that can separate an architecturenBlock nProcessExample of Block(BLKBLK.vhd)library ieee;use ieee.std_logic_1164.all;-entity blkblk is port(X:in std_logic;Y:out std_logic);end blkblk;architecturearchitecture blkblk_arch ofo

25、f blkblk is is signal A,B:std_logic;beginbegin u1:blocku1:block signal C,D:std_logic;beginbegin A=C;B=D;C=X;D=X;end block u1;end block u1;u2:blocku2:block signal C,E:std_logic;beginbegin C=A;E=B;u3:blocku3:block signal E,F,G:std_logic;begin begin E=A;F=E;G=u2.E;end block u3;end block u3;end block u2

26、;end block u2;Y=X and(A or B);endend blkblk_arch;Definition of BlockBlockLabel:block(GuardExpression)is Declarations;begin ConcurrentStatements;end block BlockLabel;Example of Block(BLKBLK.vhd)library ieee;use ieee.std_logic_1164.all;-entity blkblk is port(X:in std_logic;Y:out std_logic);end blkblk;

27、architecturearchitecture blkblk_arch ofof blkblk is is signal A,B:std_logic;beginbegin u1:blocku1:block signal C,D:std_logic;beginbegin A=C;B=D;C=X;D=X;end block u1;end block u1;u2:blocku2:block signal C,E:std_logic;beginbegin C=A;E=B;u3:blocku3:block signal E,F,G:std_logic;begin begin E=A;F=E;G=u2.

28、E;end block u3;end block u3;end block u2;end block u2;Y=X and(A or B);endend blkblk_arch;Example of Block(Test_16.vhd)begin begin Blck_Test_1:blockblock(clock=1 and ClockEVENT)beginbegin Destination_1=guarded Source;Destination_2=Source;end blockend block Blck_Test_1;Blck_Test_2:blockblock(Clock=1 a

29、nd not(ClockSTABLE)begin begin Destination_3=guarded Source;Destination_4=Source;end blockend block Blck_Test_2;Monitor:processprocessvariable Source_Var:NATURAL;variable Dest_1_Var,Dest_2_Var:NATURAL;variable Dest_3_Var,Dest_4_VAr:NATURAL begin begin Source_Var:=Source;Dest_1_Var:=Destination_1;Des

30、t_2_Var:=Destination_2;Dest_3_Var:=Destination_3;Dest_4_Var:=Destination_4;wait on Destination_1,Destination_2,Destination_3,Destination_4;end processend process Monitor;Tick_Tock:processprocess beginbeginwait for 10 ns;Clock=not clock;end processend process Tick_Tock;Source_Wave:Source=1 after 8 ns

31、,2 after 15 ns,3 after 16 ns,4 after 17 ns,5 after 18 ns,6 after 19 ns;endend Behave_1;entityentity Test_16 is isendend Test_16;architecture architecture Behave_1 ofof Test_16 is is signal Source:NATURAL:=0;signal Destination_1:NATURAL:=0;signal Destination_2:NATURAL:=0;signal Destination_3:NATURAL:

32、=0;signal Destination_4:NATURAL:=0;signal Clock:BIT:=0;Guarded Signals In BlockBlockLabel:block(GuardExpression)is Declarations;begin ConcurrentStatements;end block BlockLabel;Guarded Signals Example(LT1.vhd)library ieee;use ieee.std_logic_1164.all;entityentity LT1 is is port (D,CLK :in bit;Q :out b

33、it;Free_in :in bit;Free_out :out bit);endend LT1;architecturearchitecture LT1_arch of of LT1 is isbegin U1:blockblock beginbegin Q=guarded D;Free_out=not Free_in;end blockend block U1;endend LT1_arch;Q=D;Free_out=not Free_in;DCLKFree_inQFree_outGuarded Signals Example(LT.vhd)library ieee;use ieee.st

34、d_logic_1164.all;entityentity LT is is port (D,CLK :in bit;Q :out bit;Free_in :in bit;Free_out :out bit);endend LT;architecturearchitecture LT_arch of of LT is isbegin U1:blockblock (CLK=1)(CLK=1)beginbegin Q=guardedguarded D;Free_out=not Free_in;end blockend block U1;endend LT_arch;Q=guarded D;Free

35、_out=not Free_in;LatchDCLKFree_inQFree_outGuarded Signals Example(Wave)AgendanOverviewnEntityn nArchitectureArchitecturenKeywordsnBlockn nProcessProcessnSubprogramnFunctionnProcedurenLibrary&UsenPackage nConfigurationProcess Definitionprocess_label:process(sensitivity_list)is process_declarative_par

36、tbegin process_statement_partend process process_label;Example of Process(Test_16.vhd)begin begin Blck_Test_1:blockblock(clock=1 and ClockEVENT)beginbegin Destination_1=guarded Source;Destination_2=Source;end blockend block Blck_Test_1;Blck_Test_2:blockblock(Clock=1 and not(ClockSTABLE)begin begin D

37、estination_3=guarded Source;Destination_4=Source;end blockend block Blck_Test_2;Monitor:processprocessvariable Source_Var:NATURAL;variable Dest_1_Var,Dest_2_Var:NATURAL;variable Dest_3_Var,Dest_4_VAr:NATURAL begin begin Source_Var:=Source;Dest_1_Var:=Destination_1;Dest_2_Var:=Destination_2;Dest_3_Va

38、r:=Destination_3;Dest_4_Var:=Destination_4;wait on Destination_1,Destination_2,Destination_3,Destination_4;end processend process Monitor;Tick_Tock:processprocess beginbeginwait for 10 ns;Clock=not clock;end processend process Tick_Tock;Source_Wave:Source=1 after 8 ns,2 after 15 ns,3 after 16 ns,4 a

39、fter 17 ns,5 after 18 ns,6 after 19 ns;endend Behave_1;entityentity Test_16 is isendend Test_16;architecture architecture Behave_1 ofof Test_16 is is signal Source:NATURAL:=0;signal Destination_1:NATURAL:=0;signal Destination_2:NATURAL:=0;signal Destination_3:NATURAL:=0;signal Destination_4:NATURAL:

40、=0;signal Clock:BIT:=0;Example of Process(Test_16.vhd zoom)Monitor:processvariable Source_Var:NATURAL;variable Dest_1_Var,Dest_2_Var:NATURAL;variable Dest_3_Var,Dest_4_VAr:NATURAL begin Source_Var:=Source;Dest_1_Var:=Destination_1;Dest_2_Var:=Destination_2;Dest_3_Var:=Destination_3;Dest_4_Var:=Desti

41、nation_4;wait on Destination_1,Destination_2,Destination_3,Destination_4;end process Monitor;Tick_Tock:process beginwait for 10 ns;Clock=not clock;end process Tick_Tock;Process Example With Sensitive Table(MY_DFF.vhd)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_

42、logic_unsigned.all;-entity MY_DFF is port (D,CP :in std_logic;Q :out std_logic );end MY_DFF;architecturearchitecture MY_DFF_arch ofof MY_DFF is isbeginbegin process(CP)begin if rising_edge(CP)then Q=D;end if;end process;endend MY_DFF_arch;D Q CLKProcess Example With Wait(MY_DFF.vhd)architecturearchi

43、tecture MY_DFF_arch ofof MY_DFF is isbeginbegin processprocess beginbegin wait until CPevent and CP=1;Q=D;end process;end process;endend MY_DFF_arch;D Q CLKProcess Example(Latch.vhd)library ieee;use ieee.std_logic_1164.all;-entity LT is port (D,CLK :in bit;Q :out bit );end LT;architecturearchitectur

44、e LT_arch ofof LT is isbeginbegin process(CLK,D)begin if CLK=1 then Q=D;end if;end process;endend LT_arch;D Q CLKDCLKQProcess(PROC2 Diagram)Process Example(Proc2.vhd)library ieee;use ieee.std_logic_1164.all;-entity PROC2 is port(X:in std_logic);end PROC2;architecturearchitecture PROC2_arch ofof PROC

45、2 is is signal to_a,to_b:std_logic:=0;beginbegin PA:process(X,to_a)begin if(Xevent and X=1)or (to_aevent and to_a=1)then to_b=1 after 20ns,0 after 30ns;end if;end process PA;PB:process(to_b)begin if(to_bevent and to_b=1)then to_a=1 after 10ns,0 after 20ns;end if;end process PB;endend PROC2_arch;PA:p

46、rocess(X,to_a)begin if(Xevent and X=1)or (to_aevent and to_a=1)then to_b=1 after 20ns,0 after 30ns;end if;end process PA;PB:process(to_b)begin if(to_bevent and to_b=1)then to_a=1 after 10ns,0 after 20ns;end if;end process PB;脉冲生成器脉冲生成器 PA 脉冲生成器脉冲生成器 PB to_b to_a X Process Example(Proc2 Wave)脉冲生成器 PA

47、 脉冲生成器 PB to_b to_a X AgendanOverviewnEntityn nArchitectureArchitecturenKeywordsnBlocknProcessn nSubprogramSubprogramn nFunctionFunctionnProcedurenLibrary&UsenPackage nConfigurationFunction Definition function Name(ParamList)return Type;function Name(ParamList)return Type is DeclarativePart;begin St

48、atementPart;end function Name;DeclarationBodyFunctions Example(My_Package.vhd)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;-packagepackage my_package is isendend my_package;functionfunction SUM2SUM2(S1,S2:in std_logic_vector)returnreturn std_l

49、ogic_vector;packagepackage bodybody my_package is isendend my_package;functionfunction SUM2SUM2(S1,S2:in std_logic_vector)returnreturn std_logic_vector is is variable tmp:std_logic_vector(S1range);beginbegin tmp:=S1+S2;return tmp;endend SUM2SUM2;Function Call Examplelibrary ieee;use ieee.std_logic_1

50、164.all;library work;use work.my_package.all;-entity SUBPROC is port(X :in std_logic_vector(3 downto 0);Y :in std_logic_vector(3 downto 0);Z :out std_logic_vector(3 downto 0);end SUBPROC;architecturearchitecture SUBPROC_arch ofof SUBPROC is isbeginbegin Z=SUM2(X,Y);endend SUBPROC_arch;XYZAgendanOver