【精品】soc设计方法与实现第四章 架构设计（可编辑.ppt

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1、SoC设计方法与实现第四章 架构设计OutlinesSystem designCommonly used cores and busesWhat&Why ESL design ESL design MethodologyESL design stagesTransaction Level Modeling and standardWhat ESL design tool doSummaryExample of Hardware System ArchitectureSource:ARM Ltd.SoC design includesnSystem architecture designnSof

2、tware structure designnHardware design(chip design)Key system Architecture QuestionsApplication analysisnWhich processor should I choose?Hardware/Software partitioningnWhat is in hardware,what is in software?Bus and memory architecturenHow do I implement the control stream?nHow do I implement the da

3、ta stream?Commonly Used Buses cont.IBMs CoreConnect Commonly Used Buses cont.Silicores Wishbonen4 kind of interconnections:nPoint-to-point,data flow,shared bus,crossbar switchOCP(Open Core Protocol)BusAvalon BusDeveloped by Altera for Nios core on FPGAMulti-processor SoC(MPSoC)TIs DaVinci:ARM+DSP Bl

4、ock diagram of TMS320DM6446/3 for multimedia applicationSource:TIMPSoC cont.TIs DaVinci:Source sharing and communication between two coresSource:TIOutlinesSystem designCommonly used cores and busesWhat&Why ESL design ESL design MethodologyESL design stagesTransaction Level Modeling and standardWhat

5、ESL design tool doSummarySystem level Design ChallengesHow do I understand performance of key IP blocks before designing?nSystem-on-Chip does not mean to simply put IP into a chipHow to build an optimized system?nA system means software+hardwareComplexity Drive ESL Design90nm SoCnTwo or three of mic

6、roprocessors and more DSPsnConsiderably more memorynMore complex communication protocols Software Drive ESL Solution2006 State of Embedded Market Survey:n“the majority of embedded design projects are running behind schedule or have been cancelled”Twenty years ago,the typical embedded device probably

7、 ran 10,000 to 15,000 lines of software code;these days,two or three million lines is more the norm.The only way to overturn this alarming trend and get costs and schedules under control is to start developing and debugging the software earlier,before the hardware is available.In 65%of the design fa

8、ils,reason cited:“Limited visibility into the complete system”ESL DesignUsing high-level modeling,Transaction Level Modeling(TLM),and simulation techniques to create an“executable specification”of the design or a“virtual platform”for both software and hardware engineers Why ESL Design?Instruction Se

9、t Simulator(ISS)for software development nIncomplete from hardware perspectiveRTL simulation nAt late design stage,too slow for software development Why ESL Design?cont.Transaction Level Modeling(TLM)techniques nUse function calls,rather than signals or wires,to communicate between modules ESL desig

10、n based on TLM nGet executable platform model fasternSimulation speed 100k cycles/secESL design enabling:nSystem-level designnPre-silicon embedded software designnHardware Architecture explorationnVirtual prototypingnCo-simulation/co-verificationOutlinesSystem designCommonly used cores and busesWhy

11、ESL design ESL design methodologyESL design stagesTransaction Level Modeling and standardWhat ESL design tool doSummaryESL Design FlowDetailed ESL Design Flow(1)“Y-chart”Detailed ESL Design Flow(2)Platform based designOutlinesSystem designCommonly used cores and busesWhy ESL design ESL design method

12、ologyESL design stagesTransaction Level Modeling and standardWhat ESL design tool doSummaryESL Design Stages System architecture design stages:nFunctional designnApplication-driven architectural designnPlatform-based architecture designESL Design Stages cont.Functional designnDesign objective:nDefin

13、e the right functionalitiesnDesign problems:n What input/output?What behavior for each active components?What behavior for test scenarios to verify the system function?nActivities and models:nCreate&verify a functional model of this applicationESL Design Stage cont.Application-driven architectural d

14、esignnDesign objective:nDefine the right architecture for right application that meet cost&performance constraintnDesign problems:nHow many processors?What functions in HW/SW?What processor characteristics?What interconnection characteristics?nActivities and models:nCreate a high-level description o

15、f the platformnMap the functional application on the platformnVerify the resulting architectural modelnFind the optimal platformESL Design Stage cont.Platform-based architecture designnDesign objective:nDeliver a virtual prototype of HW platformnDesign problems:nwhat kind of processors?How much memo

16、ry?How many cache hits or misses?What bus occupancy,transaction and contention?What processor utilization for software task?How to optimize power consumption?nActivities and models:nCreate low-level description of the platformnFine tune the hardware architectureOutlinesSystem designCommonly used cor

17、es and busesWhy ESL design ESL design MethodologyESL design stagesTransaction Level Modeling and standardWhat ESL design tool doSummaryAbstraction Levels Abstraction level is largely related to the design stage and the simulator of the toolsnThe higher,the easier to writenThe higher,the faster to si

18、mulateAbstraction LevelsUn-timed function(UTF)model nFor algorithm designnNo timing informationnNo relation with the system architecturenNo relation with implementation Transaction Level Model(TLM)nBetter to describe the function of the systemnEfficient for functional verification RTL modelnDetailed

19、 chip level implementationTransaction Level ModelingTransaction:exchange of a data or an event between two components of a modeled and simulated systemTLM StandardDefined by OCP-IP(Open Core Protocol International Partnership)Defined by OSCI(Open SystemC Initiative)Defined by both OSCI&OCP-IP Abstra

20、ction Levels defined by OCP-IPAbstraction levels defined by OCP-IP Massage layer(L 3)Resource sharing,timeTransaction Layer(L-2)Clocks,protocolsTransfer layer(L 1)Wires,registersRTL Layer(L 0)Gates,gate/wire delayOCP-IP Abstraction Levels cont.Message level,application levelnProof of concept tools,r

21、ationalize 1st order functional partitioningnEvent driven modelnC.C+,SystemCTransaction level,platform levelnCarry out HW performance analysis,HW/SW partitioning,co-developmentnEvent driven model with cycle approximatenSystemCTransfer level,platform levelnPerform detailed modeling tasks.No requireme

22、nt on accurate per interface signalnClocked cycle accurate model(CA)nSystemC,SystemVerilogRegister transfer level,physical levelnVerilog,VHDLAbstraction Levels Defined by OSCIAbstraction levels defined by OSCIAbstraction Levels Defined by OSCI-contThree TLM abstracts:nProgrammers View(PV)ncontains n

23、o timingnProgrammers View with Timing(PVT)n adds timed protocols and can analyze latency or throughputnCycle Accurate(CA)naccurate to the clock edge but does not model internal registers TLM Defined by OSCI&OCP-IPJune 2004:OSCI/OCP-IP TLM Standardization Alliance Tree levels of TLM defined by both O

24、SCI and OCP-IPProgrammers View(PV)Enable embedded software designArchitects View(AV)Architecture explorationVerification View(VV)Enable HW-SW and system verificationOSCIs TLM Standards Open SystemC Initiative(OSCI)delivers SystemC TLM Standard 1.0 on June,2005 nDefine application programming interfa

25、ces(APIs)nStandard SystemC TLM librarynBut does not define the content of the transactions OSCI and OCP-IP are working together on TLM standard 2.0Design Flow vs.TLMMay need several intermediate models in a system design nSpeed of developing the modelnSpeed of the simulation of the modelnAccuracy of

26、 the modelExample:different flows from A to FA.specification modelB.Component-assembly modelC.Bus-arbitration modelD.Bus-functional modelE.Cycle-accurate computation modelF.Implementation modelSystem Modeling graphSource:Transaction Level Modeling:An Overview,by Lukai cai,etc.Model Speed vs.TLM ESL

27、DesignESL design Language SystemC and SystemVerilog n60%-90%TLM use SystemC currentlynSystemVerilog has some limitation for TLM OSCI TLM standard is based on SystemCSystemC OverviewC+library aimed specifically at system level modeling SystemC1.0 just another HDL,not much to do with system level desi

28、gnSystemC 2.0 became a system level language with the adding of channels for communicating transactionsSystemC 2.1 adding some programming language features and simulation semanticsSystemC and SystemVerilogSystemC nIEEE approved OSCI SystemC 2.1 as an IEEE 1666 standard in December,2005nSystemC is d

29、eveloped from C+nSystemC is used to design the main specifications SystemVerilog nIEEE approved Accellera SystemVerilog 3.1a as an IEEE 1800 standard in November,2005nSystemVerilog is developed from VerilognSystemVerilog is more like Verilog plus verification(assertion)nSystemVerilog is used to desi

30、gn the system-level hardwareVerilog,SystemVerilog and SystemCSoftware and embedded programmingObject oriented programmingBehavioral and transaction modelingRTL modelingGate level modelingVHDLVerilogSystem-VerilogSystemCTLM IP More and more TLM IP in SystemC available nowadays:nAMBA(AHB,APB,Periphera

31、ls)SystemC Library from Synopsys,Inc.nARM Processor SystemC Library from CoWare Inc.nCEVA processors TLM SystemC Lirary from Coware Inc.OutlinesSystem designCommonly used cores and busesWhy ESL design ESL design MethodologyESL design stagesTransaction Level Modeling and standardWhat ESL design tool

32、do SummaryExample:what we did Project task:H.264 Encoding ESL tool:ARMs MaxSim(SoC Designer)Set up ARM926 based ESL platform Port open source H.264 C code to ESL platformGet information of system performance Software Profile Optimize Architecture Hardware/Software PartitionNew model design(SystenC)H

33、ardware/Software co-verification on the ESL PlatformSoftware DesignExample cont.Structure optimizationExample cont.Software profilingDebug capability Example cont.For software developmentMonitor data cache performanceExample cont.Bus throughputnAccurate bus profilingnDetermine bus structureExample-c

34、ontFunction profilingExample-cont.Software profiling find bottlenecksnRefine Sub-pixel Interpolation in Inter Frame ModenRefine_subpel:search the pixel mv search nInterpolation of pixel blocks nBlocks operations(sum(abs(A-B)nAbout 50.35%of total encoding time on itnfrom the benchmark foreman.qcif se

35、quence at the arm system(380 frames)nPrefer for Hardware implementation(tap filter)nWe are doing the hardware implementation of this block now.Example cont.Software profiling find bottlenecks 2D integer transformnComputing intensive processnBetter for hardware implementationn4 x 4 2D Integer Transfo

36、rm in H.264:Example cont.Proposed parallel architectureExample cont.Hardware Implementation pipelined architecturenImplemented by adder and shifter nOnly need 4 cycles for 2D ICTSummaryESL design refers to a set of SoC design tasksnEmbedded software development and debugnArchitecture definitionnHW/S

37、W integrationnHW and SW performance analysis and validationUsing ESL,these tasks are performed by means of a TLM of SoC platform withnAcceptable accuracynHigh simulation speednVisibilitynFlexibility“ESL design is a highly-effective approach for creating complex chips and systems.ESL design has mainstreamedit is now an established design methodology at most of the worlds leading system-on-chip(SoC)design companies,and it is being used increasingly in system design.“SoC设计方法与实现设计方法与实现郭炜郭炜 郭筝郭筝 谢憬谢憬Thank you