数字电路第六章.ppt

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1、Chapter Chapter 4 4 Combinational Logic Combinational Logic Design PrinciplesDesign Principles(组合逻辑设计原理组合逻辑设计原理)Basic Logic Algebra (逻辑代数基础逻辑代数基础)Combinational-Circuit Analysis (组合电路分析组合电路分析)Combinational-Circuit Synthesis (组合电路综合组合电路综合)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)1 1A Cl

2、ass Problem (A Class Problem (每课一题每课一题 )将下列函数化为最简与或函数式。将下列函数化为最简与或函数式。给定约束条件为给定约束条件为Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)2 2ABCD00 01 11 100001111011111111 Finding Static Hazards Using Maps Finding Static Hazards Using Maps(利用卡诺图发现并消除静态冒险利用卡诺图发现并消除静态冒险)Digital Logic Design and App

3、lication(数字逻辑设计及应用数字逻辑设计及应用)A Class Problem (A Class Problem (每课一题每课一题 )3 3第四章第四章 组合逻辑设计原理组合逻辑设计原理开关代数开关代数公理、定理、逻辑函数的表示公理、定理、逻辑函数的表示组合电路分析组合电路分析得到指定电路的功能（公式法化简）得到指定电路的功能（公式法化简）组合电路综合组合电路综合根据命题，得到电路实现（卡诺图化简）根据命题，得到电路实现（卡诺图化简）定时冒险定时冒险Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)4 4思考：五变量如何利

4、用卡诺图化简？思考：五变量如何利用卡诺图化简？DEBC00 01 11 1000011110A=0DEBC00 01 11 1000011110A=1041215139371526141081116171918202123222829313024252726Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)5 5F=A,B,C,D,E(0,1,2,3,4,5,10,11,14,20,21,24,25,26,27,28,29,30)DEBC00 01 11 1000011110A=0DEBC00 01 11 1000011110A=1

5、111111111111111111F=+ABDACDACDABCBDEDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)6 6Chapter 6Chapter 6 Combinational Logic Design Combinational Logic Design PracticesPractices(组合逻辑设计实践组合逻辑设计实践)Documentation Standard and Circuit Timing(文档标准和电路定时文档标准和电路定时)Commonly Used MSI Combinational Log

6、ic Device(常用的中规模组合逻辑器件常用的中规模组合逻辑器件)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)7 7第第6 6章教学大纲要求章教学大纲要求 重点学习掌握：学习利用重点学习掌握：学习利用基本的逻辑门基本的逻辑门完成规定的完成规定的组合逻辑电路的组合逻辑电路的设计设计任务：如译码器、编码器、多路选任务：如译码器、编码器、多路选择器、多路分配器、异或门、比较器、全加器。学习利择器、多路分配器、异或门、比较器、全加器。学习利用基本的逻辑门和已有的中规模集成电路（用基本的逻辑门和已有的中规模集成电路（MSIMSI）逻

7、辑器逻辑器件如件如译码器译码器、编码器、编码器、多路选择器多路选择器、多路分配器、异或、多路分配器、异或门、比较器、门、比较器、全加器全加器、三态器件等作为设计的基本元素、三态器件等作为设计的基本元素完成更为复杂的组合逻辑电路完成更为复杂的组合逻辑电路设计设计的方法。的方法。Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)8 86.1 Documentation Standard6.1 Documentation Standard(文档标准文档标准)Structure Thinking(结构化的理念结构化的理念)Specifica

8、tion:Description of Interface and Function (说明书说明书：接口及功能描述接口及功能描述)Block Diagram:Systems Major Function Module and their Basic Interconnections (方框图方框图：主要功能模块及其互联主要功能模块及其互联 Figure 6-1)Schematic Diagram 原理图原理图（Figure 6-17）Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)9 96.1.1 Documentation S

9、tandard6.1.1 Documentation Standard(文档标准文档标准)Timing Diagram 定时图定时图（Figure 6-19）Structure Logic Device Description (结构化逻辑器件描述结构化逻辑器件描述)Circuit Description:Explains how the circuit works internally.(电路描述：电路描述：解释电路内部如何工作解释电路内部如何工作)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)10106.1.2 Gate S

10、ymbols(6.1.2 Gate Symbols(门的符号门的符号)&11Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)11 11Equivalent Gate Symbols underEquivalent Gate Symbols underthe Generalized the Generalized DemorgansDemorgans Theorem Theorem 等效门符号等效门符号（摩根定理）（摩根定理）Inverter(反相器反相器)Buffer(缓冲器缓冲器)12126.1.3 Signal Name an

11、d Active Levels 6.1.3 Signal Name and Active Levels(信号名和有效电平信号名和有效电平)Name a Signal(信号的命名信号的命名)An Active Level Associated with a Signal (与信号相关的有效电平与信号相关的有效电平)Active High（高电平有效（高电平有效）Active Low （低电平有效（低电平有效）Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)Asserted (有效）有效）Deasserted（无效）（无效）Negat

12、ed（取消）（取消）1313An Inversion Bubble to Indicate an Active-Low Pin(有反相圈的引脚有反相圈的引脚 表示低电平有效表示低电平有效)Given Logic Function as Occurring inside that symbolic outline.(给定逻辑功能只在符号框的内部发生给定逻辑功能只在符号框的内部发生)READYREQUESTGOREADY_LREQUEST_LGO_L6.1.3 Signal Name and Active Levels 6.1.3 Signal Name and Active Levels(信号名

13、和有效电平信号名和有效电平)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)Figure 6-5,6,7,8,9,1014146.1.5 Bubble-to-Bubble Logic Design6.1.5 Bubble-to-Bubble Logic Design(“(“圈到圈圈到圈”的逻辑设计的逻辑设计)Figure 6-11Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)15156.2 Circuit Timing(6.2 Circuit Timing(电路定时

14、电路定时)Propagation Delay(传播延迟传播延迟)A Signal Path as the Time that it takes for a Change at the Input to Produce a Change at the Output of the Path(信号通路输入端的变化引起输出端变化所需的时间信号通路输入端的变化引起输出端变化所需的时间)t tpHLpHL and and t tpLHpLH Maybe DifferentMaybe DifferentDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及

15、应用)Figure 6-191616Propagation Delay(传播延迟传播延迟)Timing Analysis:Worst-Case Delay(定时分析：取最坏情况延迟定时分析：取最坏情况延迟)Maximum Delay(最大延迟最大延迟)Typical Delay(典型延迟典型延迟)Minimum Delay(最小延迟最小延迟)080804323232表表 6-26-2152022226.2 Circuit Timing(6.2 Circuit Timing(电路定时电路定时)t tpHLpHL and and t tpLHpLH Maybe DifferentMaybe Dif

16、ferentDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)1717Timing Diagram定时图（时序图）定时图（时序图）GOREADYDATtDATtDATGOREADYDATtRDYtRDY6.2 Circuit Timing(6.2 Circuit Timing(电路定时电路定时)Causality and Propagation Delay (因果性和因果性和传播延播延迟）Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)1818GOREADYDATGOR

17、EADYDATtRDYmintRDYmax6.2 Circuit Timing(6.2 Circuit Timing(电路定时电路定时)Timing Diagram定时图（时序图）定时图（时序图）Minimum and Maximum Delay (最小和最大延最小和最大延迟）Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)1919WRITE_LDATAOUTDATAINtOUTmaxtsetuptOUTmin6.2 Circuit Timing(6.2 Circuit Timing(电路定时电路定时)Certain and Un

18、certain Transitions (确切的和不确切的确切的和不确切的转换）Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)2020Commonly Used MSI Combinational Commonly Used MSI Combinational Logic DeviceLogic Device（常用中规模组合逻辑器件）（常用中规模组合逻辑器件）Encoders(编码器编码器)Decoders(译码器译码器)Multiplexers(多路复用器多路复用器)Parity Circuits(奇偶校验奇偶校验)Compa

19、rators(比较器比较器)Adders(加法器加法器)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)2121Decoder and EncoderDecoder and Encoder(译码器和编码器译码器和编码器)Multiple-Input,Multiple-Output Logic Circuit(多输入、多输出电路多输入、多输出电路)Enable Inputs(使能输入使能输入)(输入输入编码编码)(输出输出编码编码)Map 映射映射Enable Inputs must be Asserted to perform N

20、ormal Mapping Function(使能输入有效才能使能输入有效才能实现正常映射功能实现正常映射功能)Input Cord WordOutput Cord WordDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)2222DecoderDecoder（译码器（译码器）Normally Output Code has More bits than its Input Code (一般来说，输出编码比输入编码位数多一般来说，输出编码比输入编码位数多)EncoderEncoder（编码器（编码器）Output Code has

21、Fewer bits than its Input Code called an Encoder(输出编码比输入编码位数少，则常称为编码器输出编码比输入编码位数少，则常称为编码器)Decoder and EncoderDecoder and Encoder(译码器和编码器译码器和编码器)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)2323Most Commonly Used CaseMost Commonly Used Case(一种最常用的情况一种最常用的情况)使能使能输入输入编码编码输出输出编码编码Map 映射映射Deco

22、derDecoder（译码器（译码器）EncoderEncoder（编码器（编码器）N-Bit Binary Code(n位二进制码位二进制码)2n 中取中取1码码使能使能输入输入编码编码输出输出编码编码Map 映射映射2n中取中取1码码n位二进制码位二进制码(One-out-of 2n)Table 6-4,Figure 6-32Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)24246.4 6.4 Decoder（译码器译码器）Binary Decoder (二进制译码器二进制译码器)2-to-4DecoderY0Y1Y2Y3I

23、0I1EN 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0InputsEN I1 I2Outputs Y3 Y2 Y1 Y0(2-4(2-4二进制译码器真值表二进制译码器真值表 )Truth Table for a 2-to-4 Binary DecoderDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)2525 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1

24、0 0 0InputsEN I1 I2Outputs Y3 Y2 Y1 Y0(2-4(2-4二进制译码器真值表二进制译码器真值表 )Y0=EN (I1 I2)Y1=EN (I1 I2)Y2=EN (I1 I2)Y3=EN (I1 I2)Yi=EN mi6.4 Decoder6.4 Decoder（译码器（译码器）Truth Table for a 2-to-4 Binary DecoderDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)26260 0 0 0 0 0 0 10 0 0 0 0 0 1 00 0 0 0 0 1 0

25、00 0 0 0 1 0 0 00 0 0 1 0 0 0 00 0 1 0 0 0 0 00 1 0 0 0 0 0 01 0 0 0 0 0 0 00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1I2I1I0Y7Y1Y0Y2Y3Y4Y5Y6(3-8(3-8二进制译码器真值表二进制译码器真值表)3-3-to-8to-8DecoderDecoderI2I1I0Y0Y1Y7Yi=EN mi1 1 1 1 1 1 1 01 1 1 1 1 1 0 11 1 1 1 1 0 1 11 1 1 1 0 1 1 11 1 1 0 1 1 1 11 1 0 1 1 1 1

26、11 0 1 1 1 1 1 10 1 1 1 1 1 1 16.4 Decoder6.4 Decoder（译码器（译码器）Truth Table for a 3-to-8 Binary DecoderDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)2727 Logic Symbols for Large-Scale Element(Logic Symbols for Large-Scale Element(大大规模元件的逻辑符号规模元件的逻辑符号)Y0Y1Y2Y3GAB1/2 74x139Y0Y1Y2Y3GAB1/2 74x13

27、9Y0Y1Y2Y3GAB1/2 74x139G_LABY0_LY1_LY2_LY3_LDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)Figure 6-362828The The 7474x139 Dual x139 Dual 2-2-to-4 Decoderto-4 Decoder(双双2-42-4译码器译码器7474x139)x139)74x139 1 X X 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1InputsG B AOutputs Y3

28、_L Y2_L Y1_L Y0_L(1/2 74x139双双2-4译码器真值表译码器真值表 )Truth Table for One-half of a 74x139Dual 2-to-4 Decoder2929The The 7474x138 3-to-8 Decoderx138 3-to-8 Decoder(3-8(3-8译码器译码器7474x138)x138)G1G2A_LG2B_LY3=G1 G2A G2B C B AEnable(使使 能能)Select(选选 择择)Y3_L=Y3=(G1 G2A_L G2B_L CBA)=G1+G2A_L+G2B_L+C+B+ADigital Lo

29、gic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)Figure 6-34,353030第六章第六章 作业作业6.9 6.106.13 6.166.17Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)3131Using Using the the information information given given in in Table Table 5-2 5-2 with with 74HCTxx,74AHCTxx 74HCTxx,74AHCTxx and and 74LSxx,74LSxx,Determine Determine the the exact exact maximum maximum propagation propagation delay delay from from IN IN to to OUT OUT of of the the following following Circuit.Circuit.Compare Compare and and Comment Comment on on your your results.results.A Class Problem (A Class Problem (每课一题每课一题 )3232