运放基本仿真步骤课件.ppt

《运放基本仿真步骤课件.ppt》由会员分享，可在线阅读，更多相关《运放基本仿真步骤课件.ppt（49页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、折叠式级联运放的仿真1 1a aThe Typical Performance of Op-AmpThe Typical Performance of Op-Ampn nOpen-Loop Differential Gain(AOpen-Loop Differential Gain(AV V)n nCommon-mode Rejection Ratio(CMRR)Common-mode Rejection Ratio(CMRR)n nPower Signal Rejection Ratio(PSRR)Power Signal Rejection Ratio(PSRR)n nPhase Marg

2、in(PM)Phase Margin(PM)n nInput Common Mode RangeInput Common Mode Range(ICMR)(ICMR)n nOutput Swing RangeOutput Swing Range(OSR)(OSR)n nInput/Output Impedance(CInput/Output Impedance(CININ/R/ROUTOUT)n nSlew RateSlew Raten nNoiseNoise2 2a aThe Schematic of Folded Cascode Op-AmpThe Schematic of Folded

3、Cascode Op-AmpIn order to decease the power Consumption,IBIAS is only 30nA.3 3a aCreate Schematic and Symbol in SpectreCreate Schematic and Symbol in SpectreTo create a symbol of a schematic:From Design-Create Cellview-From Cellview4 4a aOpen-Loop Differential Gain Open-Loop Differential Gain n nDC

4、Sweep VP-VN (large signal)n nAC Sweep VP-VN with fixed frequency(small signal)Two methods of simulating Open-Loop Differential Gainis available in ADE(Analog Design Environment)5 5a aTest-Bench of Open-Loop Differential Gain Test-Bench of Open-Loop Differential Gain(method 1)(method 1)DC Sweep DC Sw

5、eep V VP P-V VN N (large signal)(large signal)In this method,VP=VCM_IN+x,and VN=VCM_IN-xWhere,VCM_IN is the common voltage,x is a design variables.Setup VNSetup VP6 6a aADE of Open-Loop Differential Gain ADE of Open-Loop Differential Gain(method 1)(method 1)To add a model for the simulation From ADE

6、-Setup-Model librariesTo create a DC SweepFrom ADE-Analyses-Choose-DC7 7a aWaveform of Open-Loop Differential Gain Waveform of Open-Loop Differential Gain(method(method 1)1)Where,Differential Gain is 71.56dBTo obtain VCOM_OUT From Calculator-Special Functions-ValueVOUT-VCOM_OUTTo obtain DC gain From

7、 Calculator-Special Functions-deriv8 8a aTest-Bench of Open-Loop Differential Gain Test-Bench of Open-Loop Differential Gain(method 2)(method 2)AC Sweep AC Sweep V VP P-V VN N with fixed frequency with fixed frequencySetup VNSetup VPIn this method,VP=VCM_IN+x+VAC,and VN=VCM_INWhere,VCM_IN is the inp

8、ut common voltage,x is a design variables,VAC is a AC voltage for AC Sweep.9 9a aADE of Open-Loop Differential Gain ADE of Open-Loop Differential Gain(method 2)(method 2)To add a model for the simulation From ADE-Setup-Model librariesTo create a AC SweepFrom ADE-Analyses-Choose-ACFixedFreq1010a aWav

9、eform of Open-Loop Differential Gain Waveform of Open-Loop Differential Gain(method(method 2)2)Differential Gain is 65.56dB The results of the two methods are different,In fact,method 1 is more accurate for DC gain.1111a aCommon-mode Rejection RatioCommon-mode Rejection Ratio You can get detail illu

10、stration from“CMOS Analog Circuit Design”,Phillip E.Allen,Oxford University Press,Inc.1212a aTest-Bench of CMRRTest-Bench of CMRRWhere,VCOM_IN is the input common voltage,VAC is a AC voltage for AC Sweep.1313a aADE of CMRRADE of CMRRTo add a model for the simulation From ADE-Setup-Model librariesTo

11、create a AC SweepFrom ADE-Analyses-Choose-AC1414a aWaveform of CMRRWaveform of CMRR1/CMRRCMRRTo obtain CMRR:From Calculator-1/x1/CMRR and CMRR plot directly.1515a aWaveform of CMRRWaveform of CMRRTo obtain magnitude Plot of CMRR:From Calculator-dB20Frequency response of CMRRThe CMRR is 72.14dB at lo

12、w frequency range.To obtain phase Plot of CMRR:From Calculator-phase1616a aPower Signal Rejection RatioPower Signal Rejection Ratio You can get detail illustration from“CMOS Analog Circuit Design”,Phillip E.Allen,Oxford University Press,Inc.1717a aTest-Bench of PSRRTest-Bench of PSRRWhere,VAC is a A

13、C voltage for AC Sweep,and VDC is a DC voltage 1818a aADE of PSRRADE of PSRRTo add a model for the simulation From ADE-Setup-Model librariesTo create a AC SweepFrom ADE-Analyses-Choose-AC1919a aWaveform of PSRRWaveform of PSRR1/PSRRPSRRTo obtain CMRR:From Calculator-1/x1/PSRR and PSRR plot directly.

14、2020a aWaveform of PSRRWaveform of PSRRTo obtain magnitude Plot of PSRR:From Calculator-dB20Frequency response of PSRRThe CMRR is 79.17dB at low frequency range.To obtain phase Plot of PSRR:From Calculator-phase2121a aPhase Margin of Open-loop frequency ResponsePhase Margin of Open-loop frequency Re

15、sponse Where,VCM_IN is the input common voltage,VAC is a AC voltage for AC Sweep,And CL is the loading capacitor.2222a aTest-Bench of PMTest-Bench of PMVCM_INVACThe dominant pole is controlled by CL in folded Cascode op amp.2323a aADE of PMADE of PMTo add a model for the simulation From ADE-Setup-Mo

16、del librariesTo create a AC SweepFrom ADE-Analyses-Choose-AC2424a aWaveform of PMWaveform of PMTo obtain magnitude Plot of open-loop:From Calculator-dB20open-loop frequency responseThe PM is 74o when CL is 5pf.To obtain phase Plot of open-loop:From Calculator-phase There have two poles in open-loop

17、frequencyresponse,one is the dominant pole of output net,and the another is the mirror pole caused by active current mirror.2525a aInput Common-mode RangeInput Common-mode RangeWhere,x is a design variables and CL is the loading capacitor.2626a aTest-Bench of ICMRTest-Bench of ICMR2727a aADE of ICMR

18、ADE of ICMRTo add a model for the simulation From ADE-Setup-Model librariesTo create a DC SweepFrom ADE-Analyses-Choose-DC2828a aWaveform of ICMRWaveform of ICMRICMRThe input common-mode range is 04.2V2929a aOutput Swing RangeOutput Swing RangeWhere,VCM_IN is the input common voltage,x is a design v

19、ariables.To obtain OSR3030a aTest-Bench of OSR Test-Bench of OSR DC Sweep DC Sweep V VP P-V VN N In this method,VP=VCM_IN+x,and VN=VCM_IN-xWhere,VCM_IN is the common voltage,x is a design variables.Setup VNSetup VP3131a aADE of OSR ADE of OSR To add a model for the simulation From ADE-Setup-Model li

20、brariesTo create a DC SweepFrom ADE-Analyses-Choose-DC3232a aWaveform of OSR Waveform of OSR You can get the left waveform from page 8.OSRThe output swing range is from 842.5mV to 4.381V.PS:OSR is dependence of applications and is not constant.3333a aInput CapacitorInput CapacitorWhere,VCM_IN is the

21、 input common voltage,VAC is AC voltage for AC Sweep.3434a aTest-Bench of CTest-Bench of CININVCM_INVAC3535a aADE of CADE of CININTo add a model for the simulation From ADE-Setup-Model librariesTo create a AC SweepFrom ADE-Analyses-Choose-AC3636a aWaveform of CWaveform of CININ The input capacitor i

22、s approximate of 5pf3737a aOutput ResistanceOutput Resistance The schematic of obtaining open-loop output resistance RO.The equivalent model by using Thevenin form On the op amp.Thus,simulating ROUT and knowing AV allows one to calculate the output resistance RO of the op amp.3838a aTest-Bench of RT

23、est-Bench of ROUTOUTIOUTVOUT200RR=1GVIN=0V3939a aADE of RADE of ROUTOUTTo add a model for the simulation From ADE-Setup-Model librariesTo create a TRAN SweepFrom ADE-Analyses-Choose-TRAN4040a aWaveform of RWaveform of ROUTOUT IOUTROUT4141a aSlew RateSlew Rate The unity-gain configuration places the

24、severest requirements on stabilityand slew rate because its feedback is the largest,resulting in the largest values of loop-gain,and should always be used as a worst-case measurement.4242a aTest-bench of Slew RateTest-bench of Slew RateThe input step magnitude is 2V.4343a aADE of SR ADE of SR To add

25、 a model for the simulation From ADE-Setup-Model librariesTo create a TranFrom ADE-Analyses-Choose-Tran4444a aWaveform of SRWaveform of SR SR=95.1K V/s4545a aNoise Noise n n Thermal Noise Thermal Noise (A)channel noise(id)(A)channel noise(id)(A)R (A)RS S noise(rs)noise(rs)(A)R (A)RD D noise(rd)noise

26、(rd)n n Flicker Noise(fn)Flicker Noise(fn)4646a aTest-Bench of NoiseTest-Bench of NoiseVCM_INVACThe dominant pole is controlled by CL in folded Cascode op amp.4747a aADE of NoiseADE of NoiseTo add a model for the simulation From ADE-Setup-Model librariesTo create a NoiseFrom ADE-Analyses-Choose-noise4848a aWaveform of NoiseWaveform of NoiseOutput noiseInput-referred noiseTo obtain output noise and input-referred noise:From ADE-results-Direct plot-main form4949a a