基于单片机的智能晾衣架控制系统的设计与实现外文文献原稿和译文.doc

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1、基于单片机的智能晾衣架控制系统的设计与实现外文文献原稿和译文外文文献原稿和译文原稿The Description of AT89S511 General DescriptionThe AT89S51 is a low-power, highperformance CMOS 8-bit microcontroller with 4K bytes of InSystem Programmable Flash memory. The device is manufactured using Atmels highdensity nonvolatile memory technology and is

2、 compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer。 By combining a versatile 8bit CPU with InSystem Programmable Flash on a monolithic chip, the Atmel AT89

3、S51 is a powerful microcontroller which provides a highlyflexible and cost-effective solution to many embedded control applications.The AT89S51 provides the following standard features： 4K bytes of Flash, 128 bytes of RAM， 32 I/O lines， Watchdog timer, two data pointers, two 16bit timer/counters， a

4、fivevector two-level interrupt architecture， a full duplex serial port, on-chip oscillator, and clock circuitry。 In addition， the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes。 The Idle Mode stops the CPU while allo

5、wing the RAM， timer/counters, serial port, and interrupt system to continue functioning。 The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.2 PortsPort 0 is an 8-bit open drain bidirectional I/

6、O port。 As an output port， each pin can sink eight TTL inputs。 When 1s are written to port 0 pins， the pins can be used as highimpedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode， P0 has in

7、ternal pullups。 Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification。 External pullups are required during program verification。Port 1 is an 8bit bidirectional I/O port with internal pullups。 The Port 1 output buffers can sink/source fou

8、r TTL inputs. When 1s are written to Port 1 pins， they are pulled high by the internal pullups and can be used as inputs. As inputs， Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the loworder address bytes during Fla

9、sh programming and verification.Port PinAlternate FunctionsP1。5MOSI (used for InSystem Programming)P1。6MOSO (used for InSystem Programming)P1.7 SCK（used for InSystem Programming)Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inpu

10、ts。 When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs。 As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external

11、program memory and during accesses to external data memory that use 16bit addresses （MOVX DPTR）. In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses （MOVX RI), Port 2 emits the contents of the P2 Special Function

12、 Register。 Port 2 also receives the highorder address bits and some control signals during Flash programming and verification。Port 3 is an 8bit bidirectional I/O port with internal pull-ups。 The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulle

13、d high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current （IIL） because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special f

14、eatures of the AT89S51， as shown in the following table.Port PinAlternate FunctionsP3.0RXD(serial input port)P3.1TXD(serial output port)P3。2INT0(external interrupt 0)P3。3INT1(external interrupt 1）P3。4T0(timer 0 external input)P3。5T1（timer 1 external input)P3。6WR（external data memory write strobe）P3。

15、7RD(external data memory read strobe)3 Special Function RegistersA map of the onchip memory area called the Special Function Register (SFR） space is shown in Table 3-1. Table 31。 AT89S51 SFR Map and Reset Values0F8H 0FFH 0F0H B 00000000 0F7H 0E8H 0EFH 0E0H ACC 00000000 0E7H 0D8H 0DFH 0D0H PSW 000000

16、00 0D7H 0C8H 0CFH 0C0H 0C7H 0B8H IP XX000000 0BFH 0B0H P3 11111111 0B7H 0A8H IE 0X000000 0AFH 0A0H P2 11111111 AUXR1 XXXXXXX0 WDTRST XXXXXXXX 0A7H 98H SCON 00000000 SBUF XXXXXXXX 9FH 90H P1 11111111 97H 88H TCON 00000000 TMOD 00000000 TL0 00000000 TL1 00000000 TH0 00000000 TH1 00000000 AUXR XXX00XX

17、8FH 80H P0 11111111 SP 00000111 DP0L 00000000 DP0H 00000000 DP1L 00000000 DP1H 00000000 PCON 0XXX0000 87H Note that not all of the addresses are occupied， and unoccupied addresses may not be implemented on the chip。 Read accesses to these addresses will in general return random data, and write acces

18、ses will have an indeterminate effect。 User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case， the reset or inactive values of the new bits will always be 0。 Interrupt Registers: The individual interrupt enable bi

19、ts are in the IE register。 Two priorities can be set for each of the five interrupt sources in the IP register。Table 3-2。 AUXR:Auxiliary RegisterAUXR Address=8EH Reset Value=XXX00XX0b Not Bit Addressable WDIDLE DISRTO DISALEBit 7 6 5 4 3 2 1 0 Reserved for future expansionDISALE Disable/Enable ALE D

20、ISALE Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency 1 ALE is active only during a MOVX or MOVC instruction DISRTO Disable/Enable Resetout DISRTO 0 Reset pin is driven High after WDT times out 1 Reset pin is input only WDIDLE Disable/Enable WDT in IDLE modeWDIDLE0

21、 WDT continues to count in IDLE mode 1 WDT halts counting in IDLE mode Dual Data Pointer Registers： To facilitate accessing both internal and external data memory， two banks of 16bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H85H. Bit DPS = 0 in SFR AUXR1

22、 selects DP0 and DPS = 1 selects DP1。 The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag: The Power Off Flag （POF) is located at bit 4 （PCON.4) in the PCON SFR. POF is set to “1 during power up。 It can be set an

23、d rest under software control and is not affected by reset。4 Memory OrganizationMCS51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed。4。1 Program MemoryIf the EA pin is connected to GND， all program fetches

24、are directed to external memory. On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory。4。2 Data MemoryThe AT89S51 implements 128 bytes of on-chip RAM. The

25、 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing， so the 128 bytes of data RAM are available as stack space.5 Watchdog Timer (Onetime Enabled with Reset-out） The WDT is intended as a recovery method in situations where the CPU m

26、ay be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST） SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT， a user must write 01EH and 0E1H in sequence to the WDTRST register （SFR location 0A6H）. When the WDT is enabled，

27、it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency。 There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset）. When WDT overflows， it will drive an output RESET HIGH pu

28、lse at the RST pin.5。1 Using the WDTTo enable the WDT， a user must write 01EH and 0E1H in sequence to the WDTRST register （SFR location 0A6H). When the WDT is enabled， the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14bit counter overflows when it reaches

29、 16383 (3FFFH）， and this will reset the device. When the WDT is enabled， it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles。 To reset the WDT the user must write 01EH and 0E1H to WDTRST。 WDTRST is a writeo

30、nly register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC。 To make the best use of the WDT, it should be serviced in those sections of code that will periodically be exe

31、cuted within the time required to prevent a WDT reset。5。2 WDT DURING Powerdown and IdleIn Powerdown mode the oscillator stops, which means the WDT also stops. While in Powerdown mode， the user does not need to service the WDT。 There are two methods of exiting Power-down mode： by a hardware reset or

32、via a levelactivated external interrupt， which is enabled prior to entering Powerdown mode. When Power-down is exited with hardware reset， servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Powerdown with an interrupt is significantly different. The interrupt i

33、s held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset du

34、ring the interrupt service for the interrupt used to exit Powerdown mode. To ensure that the WDT does not overflow within a few states of exiting Power-down， it is best to reset the WDT just before entering Power-down mode。 Before going into the IDLE mode， the WDIDLE bit in SFR AUXR is used to deter

35、mine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE （WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE， service the WDT， and reenter IDLE mo

36、de.With WDIDLE bit enabled， the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.6.InterruptsThe AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1）， two timer interrupts （Timers 0 and 1)， and the serial port interrupt。 These interrupts

37、 are all shown in Figure 6-1。 Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit， EA， which disables all interrupts at once。Note that Table 61 shows that bit positions IE.6 and IE

38、.5 are unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. Figure

39、 6-1 Interrupt Sources7 Oscillator Characteristics XTAL1 and XTAL2 are the input and output， respectively， of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7-1. Either a quartz crystal or ceramic resonator may be used。 To drive the device from an

40、external clock source， XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 7-2。 There are no requirements on the duty cycle of the external clock signal， since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage hi

41、gh and low time specifications must be observed.Figure 7-1 Oscillator ConnectionsNote： for Crystals for Ceramic ResonatorsFigure 7-2 External Clock Drive Configuration8 Idle Mode In idle mode， the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by softwa

42、re. The content of the onchip RAM and all the special function registers remain unchanged during this mode。 The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from

43、 where it left off， up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated

44、by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory。9 Power-down Mode In the Power-down mode, the oscillator is stopped, and the instruction that invokes Powerdown is the last instruction executed. The on-chip RAM and Special Func

45、tion Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the onchip RAM。 The reset should not be act

46、ivated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Table 9-1 Status of External Pins During Idle and Powerdown ModesModeProgram MemoryALEPSENPORT0PORT1PORT2PORT3IdleInternal 1 1DataDataDataDataIdleExternal 1 1FloatDataAddressDataPowerdownInternal 0 0DataDataDataDataPower-downExternal 0 0FloatDataDataData 12译文AT89S51概述1 一般概述 该AT89S51是一个低功耗，高