verilog交通灯设计.pdf

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1、 module jtd(zhi,clk,u,i);input zhi,clk;output 2:0u,i;reg2:0u,i;reg d;always(posedge clk)begin if(zhi)begin u2:0=3b100;i2:0=3b001;end else begin d=d+1;if(d=30)u2:0=3b010;if(d=34)begin u2:0=3b001;i2:0=3b100;end if(d=64)begin u2:0=3b001;i2:0=3b010;end if(d=68)begin u2:0=3b100;i2:0=3b001;d=0;end module

2、jtd(zhi,u,i,clk,rst);input zhi,clk,rst;output 2:0u,i;reg 2:0u,i;reg4:0state;reg 5:0d;initial d=0;parameter s0=5b00001,s1=5b00010,s2=5b00100,s3=5b01000,s4=5b10000;always(posedge clk)begin if(!rst)begin state=s0;u2:0=3b100;i2:0=3b001;end else begin case(state)s4:begin u2:0=3b100;i2:0=3b001;if(zhi)begi

3、n state=s0;end else state=s4;end s0:begin u2:0=3b100;i2:0=3b001;d=d+1;if(d=30)begin state=s1;d=0;end else state=s0;end s1:begin u2:0=3b010;i2:0=3b001;d=d+1;if(d=4)begin state=s2;d=0;end else state=s1;end s2:begin u2:0=3b001;i2:0=3b100;d=d+1;if(d=30)begin state=s3;d=0;end else state=s2;end s3:begin u

4、2:0=3b001;i2:0=3b010;d=d+1;if(d=4)begin state=s4;d=0;end else state=s3;end default:state=s4;endcase end end endmodule 黄灯闪 module jtde(zhi,u,i,clk,rst);input zhi,clk,rst;output 2:0u,i;reg 2:0u,i;reg4:0state;reg 6:0d;initial d=0;parameter s0=5b00001,s1=5b00010,s2=5b00100,s3=5b01000,s4=5b10000;always(p

5、osedge clk)begin if(!rst)begin state=s4;u2:0=3b100;i2:0=3b001;end else begin case(state)s4:begin u2:0=3b100;i2:0=3b001;if(zhi)begin state=s0;end else state=s4;end s0:begin u2:0=3b100;i2:0=3b001;d=d+1;if(d=30)begin state=s1;d=0;end else state=s0;end s1:begin d=d+1;if(d=1)begin u2:0=3b000;i2:0=3b001;s

6、tate=s1;end if(d=2)begin u2:0=3b010;i2:0=3b001;state=s1;end if(d=3)begin u2:0=3b000;i2:0=3b001;state=s1;end if(d=4)begin u2:0=3b010;i2:0=3b001;state=s2;d=0;end end s2:begin u2:0=3b001;i2:0=3b100;d=d+1;if(d=30)begin state=s3;d=0;end else state=s2;end s3:begin d=d+1;if(d=1)begin i2:0=3b000;u2:0=3b001;

7、state=s3;end if(d=2)begin i2:0=3b010;u2:0=3b001;state=s3;end if(d=3)begin i2:0=3b000;u2:0=3b001;state=s3;end if(d=4)begin i2:0=3b010;u2:0=3b001;state=s4;d=0;end end default:state=s4;endcase end end 黄灯闪且倒计时 module mnb(zhi,u,i,clk,rst,ugx,usx,igx,isx);input zhi,clk,rst;output 2:0u,i;output 3:0ugx,usx,

8、igx,isx;reg 2:0u,i;reg4:0state;reg 4:0ugx,usx,igx,isx;reg 6:0d,e,f;initial begin d=0;e=30;f=34;end parameter s0=5b00001,s1=5b00010,s2=5b00100,s3=5b01000,s4=5b10000;always(posedge clk)begin if(!rst)begin state=s4;u2:0=3b100;i2:0=3b001;end else begin case(state)s4:begin u2:0=3b100;i2:0=3b001;ugx=0;usx

9、=0;igx=0;isx=0;if(zhi)begin state=s0;d=0;e=30;f=35;end else state=s4;end s0:begin u2:0=3b100;i2:0=3b001;ugx=e%10;usx=e/10;igx=f%10;isx=f/10;d=d+1;e=e-1;f=f-1;if(d=30)begin state=s1;d=0;e=4;f=4;end else state=s0;end s1:begin ugx=e%10;usx=e/10;igx=f%10;isx=f/10;e=e-1;f=f-1;if(d=0)begin u2:0=3b010;i2:0

10、=3b001;d=d+1;state=s1;end if(d=1)begin u2:0=3b000;i2:0=3b001;d=d+1;state=s1;end if(d=2)begin u2:0=3b010;i2:0=3b001;d=d+1;state=s1;end if(d=3)begin u2:0=3b000;i2:0=3b001;state=s2;d=0;e=35;f=30;end end s2:begin u2:0=3b001;i2:0=3b100;ugx=e%10;usx=e/10;igx=f%10;isx=f/10;d=d+1;e =e-1;f=f-1;if(d=30)begin

11、state=s3;d=0;e=4;f=4;end else state=s2;end s3:begin ugx=e%10;usx=e/10;igx=f%10;isx=f/10;d=d+1;e=e-1;f=f-1;if(d=1)begin i2:0=3b000;u2:0=3b001;state=s3;end if(d=2)begin i2:0=3b010;u2:0=3b001;state=s3;end if(d=3)begin i2:0=3b000;u2:0=3b001;state=s3;end if(d=4)begin i2:0=3b010;u2:0=3b001;state=s4;d=0;end end default:state=s4;endcase end end endmodule 黄灯闪 （注：专业文档是经验性极强的领域，无法思考和涵盖全面，素材和资料部分来自网络，供参考。可复制、编制，期待你的好评与关注）