数字电路英文版第八单元.pptx

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1、Astable(非稳态的)Hold-time (保持时间)Asynchronous (异步)Bistable (双稳态)Clear (清零)D flip-flop (D 触发器)Edge-triggered flip-flop (边沿触发器)Feed-back (反馈)Hysteresis (迟滞)J-K flip-flop (JK触发器)Latch (锁存器)Master-slave flip-flop (主从触发器)第1页/共123页Monostable (单稳态)One-shot (单稳)Preset (预置1)RESET (置0)SET (置1)Set-up time (设置时间)S-

2、R flip-flop(RS触发器)Synchronous (同步)Timer (计时器)Toggle (触发,计数)第2页/共123页KEY TERMS Astable Having no stable state.An astable multivibrator oscillates between two quasistable states.Asynchronous Having no fixed time relationship.Bistable Having two stable states.Flip-flops and latches are bistable multivi

3、brators.第3页/共123页Clear An asynchronous input used to reset a flip-flop(make the Q output 0).D flip-flop A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.第4页/共123页Edge-triggered flip-flop A type of flip-flop in which the dat

4、a are entered and appear on the output on the same clock edge.Feedback The output voltage or a portion of it that is connected back to the input of a circuit.第5页/共123页Hold time The time interval required for the control levels to remain on the inputs to a flip-flop after the triggering edge of the c

5、lock in order to reliably activate the device.Latch A bistable digital circuit used for storing a bit.第6页/共123页Hystersis A characteristic of a threshold-triggered circuit,such as the Schmitt trigger,where the device turns on and off at different input levels.J-K flip-flop A type of flip-flop that ca

6、n operate in the SET,RESET,no-change,and toggle modes.第7页/共123页Master-slave flip-flop A type of flip-flop in which the input data are entered into the device on the leading edges of clock pulses and apper at the output on trailing edges.Master-slave flip-flops have,for the most part,been replaced by

7、 edge-triggered types.第8页/共123页Monostable Having only one stable state.A monostable multivibrator,commonly called a one-shot,produces a single pulse in response to a triggering input.One-shot A monostable multivibrator.Preset An asynchronous input used to set a flip-flop(make the Q output 1).第9页/共12

8、3页RESET The state of a flip-flop or latch when the output is 0;the action of producing a RESET state.SET The state of a flip-flop or latch when the output is 1;the action of producing a SET state.第10页/共123页Set-up time The time interval required for the control levels to be on the inputs to a digital

9、 circuit,such as a flip-flop,prior to the triggering edge of a clock pulse.S-R flip-flop A SET-RESET flip-flop.第11页/共123页Synchronous Having a fixed time relationship.Toggle The action of a flip-flop when it changes state on each clock pulse.第12页/共123页 8.1 LATCHES 8.1 LATCHESThe latch is a type of te

10、mporary storage device that has two stable states (bistable)and is normally placed in a category separate from that of flip-flop.2.第13页/共123页 Latches are basically similar to flip-flops because they are bistable devices that can reside in either of two states using a feedback arrangement,in which th

11、e outputs are connected back to the opposite inputs.The main difference between latches and flip-flop is in the method used for changing their state.3.第14页/共123页The S-R(SET-RESET)LatchRSQQ(a)Active-HIGH input S-R latch (NOR S-R Latch)4.第15页/共123页QQSR5VRRRRRR5.第16页/共123页SRQQ(b)Active-LOW input S-R la

12、tch (NAND S-R Latch)6.第17页/共123页SRQQWhen Q is HIGH,Q is LOW,and when Q is LOW,Q is HIGH.7.第18页/共123页第19页/共123页第20页/共123页 Input Outputs S R Q Q Comments 1 1 NC NC No change.latch remains in present state.0 1 1 0 Latch SET.1 0 0 1 Latch RESET.0 0 1 1 Invalid condition.TABLE 8-1Truth table for an activ

13、e-LOW input S-R latch.8.第21页/共123页 Input Outputs S R Q Q Comments 0 0 NC NC No change.latch remains in present state.0 1 0 1 Latch RESET.1 0 1 0 Latch SET.1 1 0 0 Invalid condition.TABLE 8-1Truth table for an active-HIGH input S-R latch.第22页/共123页SRQQ(a)Active-HIGH input S-R latchSRQQ(b)Active-LOW i

14、nput S-R latchSR9.第23页/共123页EXAMPLE 8-1SRQ10.第24页/共123页EXAMPLE 8-1:Related Problem Determine the Q output of an active-HIGH input S-R latch if the waveforms in above are inverted and applied to the input.SRQ第25页/共123页 Although S remains LOW for only a very short time before the switch bounce,this is

15、 sufficient to set the latch.第26页/共123页The Gated S-R LatchSRQQENSREN(a)Logic diagram(b)Logic symbol12.The latch will not change until EN is HIGH,but as long as it remains HIGH,the output is controlled by the state of the S and R inputs.第27页/共123页EXAMPLE 8-2 Determine the output waveform if the input

16、s shown in Fig.8-9 are applied to a gated S-R latch that is initially RESET.SRQEN13.Fig.8-9(a)(b)第28页/共123页EXAMPLE 8-2:Related Problem Determine the Q output of a gated S-R latch if the S and R inputs in Fig.8-9(a)are inverted.SRQEN13.Fig.8-9(a)(b)第29页/共123页The Gated D LatchDQQENDEN(a)Logic diagram(

17、b)Logic symbol14.QQQn+1=D(S)(R)第30页/共123页EXAMPLE 8-3 Determine the Q output waveform if the inputs shown in Fig.8-11(a)are applied to a gated D latch,which is initially RESET.DQEN15.Fig.8-11(a)第31页/共123页EXAMPLE 8-3 Related Problem Determine the Q output of the gated D latch,if the D input in Fig.8-1

18、1(a)is reverted.DQEN(a)第32页/共123页 Input Outputs D EN Q Q Comments 0 1 0 1 RESET.1 1 1 0 SET.X 0 Q0 Q0 No changeTruth table16.Qn+1=D第33页/共123页 8.2 EDGE-TRIGGERED 8.2 EDGE-TRIGGERED FLIP-FLOPSFLIP-FLOPSFlip-flops are synchronous bistable devices,also known as bistable multivibrators.In this case,the t

19、erm synchronous means that the output changes state only at a specified point on a triggering input called the clock(CLK)which is designated as a control input C;that is,changes in the output occur in synchronization with the clock.17.第34页/共123页Edge-triggered flip-flop:SRQQCDQQCJKQQCSRQQCDQQCJKQQCTo

20、p:positive edge-triggered;bottom:negative edge-triggered.18.第35页/共123页The Edge-Triggered S-R Flip-Flop:SRQQC Inputs Outputs 0 0 X Q0 Q0 No change S R CLK Q Q Comments 0 1 0 1 RESET 1 0 1 0 SET 1 1?Invalid19.Qn+1=S+RQn (SR=0 condition)第36页/共123页EXAMPLE 8-4SRQQC123456SRQCLK20.第37页/共123页EXAMPLE 8-4 Det

21、ermine Q for the S and R inputs in Fig.8-16(a)if the flip-flop is a negative edge-triggered device.123456SRQCLK第38页/共123页第39页/共123页PulsetransitiondetectorQQSRCLK01HIGH(1)LOW(0)01010101This gate is disabledBecause R is LOW.This gate is enabled.G4G3G2G1HIGHFig.8-1821.第40页/共123页PulsetransitiondetectorQ

22、QSRCLK01HIGH(1)LOW(0)01010101This gate is disabledbecause S is LOW.This gate is enabled.G4G3G2G1HIGHFig.8-1922.第41页/共123页The Edge-Triggered D Flip-Flop:SQQCDCLK Inputs Outputs 1 1 0 SET(1)D CLK Q Q Comments 0 0 1 RESET(0)23.R第42页/共123页EXAMPLE 8-5DQQC1234QDCLK24.第43页/共123页1234QDCLKEXAMPLE 8-5 Related

23、 Problem Determine the Q output for the D flip-flop if the D input in Fig.8-21(a)is reversed.第44页/共123页1234QDCLKEXAMPLE 8-5 Related Problem Determine the Q output for the D flip-flop if the D input in Fig.8-21(a)is reversed.第45页/共123页The Edge-Triggered J-K Flip-Flop:JKQQC Inputs Outputs 0 0 Q0 Q0 No

24、 change J K CLK Q Q Comments 0 1 0 1 RESET 1 0 1 0 SET 1 1 Q0 Q0 Toggle25.Qn+1=J Qn+KQn第46页/共123页 Inputs Output 0 0 0 0 J K Qn Qn+1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0Qn+1=J Qn+KQn1JKQn00011110010123456711110J=X K=1J=1 K=XJ=X K=0J=0 K=X第47页/共123页 Inputs Output 0 0 0 0 S R Qn Qn+1

25、 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 X 1 1 1 XSRQn000111100101234567110S=0 R=1S=1 R=0S=X R=0S=0 R=X11XXQn+1=S+RQn (SR=0 condition)第48页/共123页PulsetransitiondetectorQQJKA simplified logic diagram for a positive edge-triggered J-K flip-flop.G4G3G2G1CLK26.第49页/共123页PulsetransitiondetectorQQJKT

26、ransitions illustrating the toggle when J=1 and K=1.G4G3G2G1CLK123HIGHHIGH1 2 31231 2 327.第50页/共123页EXAMPLE 8-612345CLKJKQJKQQCCLKToggleNochangeResetSetSet28.Fig.8-24(a)第51页/共123页EXAMPLE 8-6 Related Problem Determine the Q output for the J-K flip-flop if the J-K inputs in Fig.8-24(a)are reversed.123

27、45CLKJKQFig.8-24第52页/共123页EXAMPLE 8-6 Related Problem Determine the Q output for the J-K flip-flop if the J-K inputs in Fig.8-24(a)are reversed.12345CLKJKQToggleNochangeResetSetReset第53页/共123页Asynchronous Preset and Clear InputsJKQQCPRECLRLogic symbol for a J-K flip-flop with active-LOW preset and c

28、lear inputs.29.第54页/共123页PulsetransitiondetectorPRECLRQQJKCLKLogic diagram for a basic J-K flip-flop with active-LOW preset and clear.30.第55页/共123页JKQQCPRECLREXAMPLE 8-8:For the positive edge-triggered J-K flip-flop,determine Q.HIGH31.第56页/共123页213456789CLRPREQPresetToggleClear32.第57页/共123页EXAMPLE 8

29、-8:Related Problem If you interchange the PRE and CLR waveforms in Fig.8-28(a),what the Q output look like.213456789CLRPREQ第58页/共123页EXAMPLE 8-8:Related Problem If you interchange the PRE and CLR waveforms in Fig.8-28(a),what the Q output look like.213456789CLRPREQPresetToggleClear第59页/共123页 88883 M

30、ASTER-SLAVE FLIP-FLOP3 MASTER-SLAVE FLIP-FLOP3 MASTER-SLAVE FLIP-FLOP3 MASTER-SLAVE FLIP-FLOPAnother class of flip-flop is the pulse-triggered master-slave,which has largely been replaced by the edge-triggered devices.Although master-slave flip-flops are essentially becoming obsolete,you may encount

31、er this type of flip-flop in some existing equipment.33.第60页/共123页Data are entered into the flip-flop at the leading edge of the clock pulses,but the output does not reflect the input state until the trailing edge.The pulse-triggered master-slave flip-flop does not allow data to change while the clo

32、ck pulse is active.34.第61页/共123页The Pulse-Triggered Master-Slave J-K flip-flopG1G2SRQQG1G2SRQQCJKCLKMasterSlave 35.第62页/共123页 Inputs Outputs 0 0 Q0 Q0 No change J K CLK Q Q Comments 0 1 0 1 RESET 1 0 1 0 SET 1 1 Q0 Q0 ToggleTruth table for the master-slaver flip-flop36.第63页/共123页JKQQCJKQQC(a)Active-

33、HIGH clock:Data are clocked in on positive-going edge of clock pulse and transferred to output on the following negative-going edge.(b)Active-LOW clock:Data are clocked in on negative-going edge of clock pulse and transferred to output on the following positive-going edge.37.第64页/共123页EXAMPLE 8-10:D

34、etermine the Q output of the master-slave J-K flip-flop for the input waveforms shown in Fig.JKQQC38.第65页/共123页567892134KJQCLKMa SSla SMa NCSla NCMa RESla REMa NCSla NCMa SSla SMa REMa RESla RESla REMa SMa SSla SSla SSETNCNCToggleReset39.第66页/共123页 88885 FLIP-FLOP APPLICATIONS5 FLIP-FLOP APPLICATION

35、S5 FLIP-FLOP APPLICATIONS5 FLIP-FLOP APPLICATIONSApplication ExampleParallel Data Storage:A common requirement in digital systems is to store several bits of data from parallel lines simultaneously in a group of flip-flop.40.第67页/共123页DDDDQ1Q0Q2Q3D0D1D2D3CLKCLRRRRRD0D1D3D20011CLKCLRQ1Q0Q2Q3000041.00

36、11CLRD stored0011第68页/共123页Frequency Division:Another application of a flip-flop is dividing the frequency of a periodic waveform.JKQCHIGHCLK213456789CLKQ42.第69页/共123页JKQACHIGHCLK213456789CLKQAJKQBCHIGHQB43.第70页/共123页JKQAC1CLK21345678CLKQAJKQBC1QBCounting110110100100001103201123Binary sequenceBinary

37、 sequence第71页/共123页EXAMPLE 8-12:Determine the output waveforms in the relation to the clock for QA,QB,QC in the below circuit.JKQAC1JKCCLKJKCQBQCQAQBQC44.第72页/共123页1CLKQAQBQC1111011111110000000000000045.第73页/共123页 8.6 ONE-SHOTS 8.6 ONE-SHOTSThe one-shot is a monostable multivibrator,a device with on

38、ly one stable state.A one-shot is normally in its stable state and will change to its unstable state only when triggered.46.第74页/共123页Once it is triggered,the one-shot remains in its unstable state for a predetermined length of time and then automatically returns to its stable state.The time that th

39、e device stays in its unstable state determines the pulse width of its output.47.第75页/共123页Triggert1t1t1t1t1t2t2t2t2RG1G2Q+VApparent LOW48.第76页/共123页QQTriggerQQCREXTCEXTTriggerCXRX/CX+VBasic one-shot logic symbols.CX and RX stand for external components.49.第77页/共123页Nonretriggerable One-Shots :It wi

40、ll not respond to any additional trigger pulses from the time it is triggered into its unstable state until it returns to its stable state.TriggerQtw(a)第78页/共123页TriggerQtwThese pulse are ignored by the one-shot.(b)50.第79页/共123页The output pulse width is set by the values of the resistor(RINT=2k,and

41、REXT is selected)and the capacitor according to the following formula:tw=0.7RCEXTR is either RINT or REXT51.第80页/共123页Retriggerable One-Shots:It can be triggered before it times out.TriggerQtw(a)第81页/共123页TriggerQtwRetriggers(b)52.第82页/共123页A general formula for calculating the values of these compo

42、nents for a specified pulse width(tw)is tw=0.32CEXT(1+0.7/R)53.第83页/共123页第84页/共123页 8.7 THE 555 TIMER 8.7 THE 555 TIMERThe 555 timer is a versatile and widely used device because it can be configured in two different modes as either a monostable multivibrator(one-shot)or as an astable multivibrator(

43、oscillator).An astable multivibrator has no stable states and therefore changes back and forth(oscillates)between two unstable states without any external triggering.54.第85页/共123页+_+_RSQQ1Comparator AComparator BThresholdControlvoltageTriggerDischargeGNDResetVccoutputDischargetransistorRRR(6)(8)(5)(

44、2)(7)(1)(4)(3)55.第86页/共123页Monostable(One-Shot)Operationtw=1.1R1C1DISCHRESETTHRESHTRIGOUTCONTGNDVccVcc(8)(4)(7)(6)(2)(1)(5)(3)R1C1C256.第87页/共123页+_+_RSQQ1ABVccoutputRRR(6)(8)(5)(2)(7)(1)(4)(3)LOWLOWH-TH0 VLOW(a)Prior to triggeringR1ON57.第88页/共123页+_+_RSQQ1ABVccRRR(6)(8)(5)(2)(7)(1)(4)(3)LOW0 V(b)Whe

45、n triggeredt0t0t0t0Vc10R1OFF58.Output第89页/共123页+_+_RSQQ1ABRRR(6)(5)(2)(7)(1)(4)LOW0 V(c)At end of charging intervalt0t0t1t0VCC0R1ONt1t1t1HIGH2359.第90页/共123页Astable OperationDISCHRESETTHRESHTRIGOUTCONTGNDVccVcc(8)(4)(7)(6)(2)(1)(5)(3)R1C1C260.R2第91页/共123页第92页/共123页+_+_RSQQ1ABRRR(6)(5)(2)(7)(1)(4)(3)0

46、 VOperation of the 555 timer in the astable modeR1ONChargingDischargingR261.2/3 Vcc1/3 Vcc(1)(1)第93页/共123页The frequency of oscillation is given by the following formula.f=1.44(R1+2R2)C1(8-4)The time that the output is HIGH(tH)is how long it takes C1 to charge from 1/3Vcc to 2/3Vcc.tH=0.7(R1+R2)C1(8-

47、5)62.第94页/共123页The time that the output is LOW(tL)is how long it takes C1 to discharge from 1/3Vcc to 2/3Vcc.tL=0.7R2C1(8-6)T=tH +tL=0.7(R1+2R2)C1Duty cycle=tHT tH tH tL+63.第95页/共123页Duty cycle=100%R1+R2 R1+2R264.(8-7)第96页/共123页Duty cycle=100%R1 R1+R2DISCHRESETTHRESHTRIGOUTCONTGNDVccVcc(8)(4)(7)(6)(

48、2)(1)(5)(3)R1C1C2D165.(8-8)R2第97页/共123页+_+_RSQQ1ABRRR(6)(5)(2)(7)(1)(4)VI Schmitt-Trigger FFVCC59.第98页/共123页6847235555(0)6847235555(0)R3R2R1S20 k5V10uFC2C10.01uF0.01uF0.22uFC32.4 k tw=10 s f=1.2 kHz Find R1,R2 第99页/共123页6847235555(0)6847235555(0)R3R2R1S20 k5V10uFC2C10.01uF0.01uF0.22uFC32.4 k tw=10 s

49、 f=1.2 kHz Find R1,R2 One Shot:tw=1.1R1C1 (8 3)Astable multivibrator:f =1.44/(R2+2R3)C2 (8-4)第100页/共123页Chapter 8:Flip-Flop and Related DevicesTrue/False 1.All multivibrators require feedback.2.Multivibrators must be level triggered.3.Edge-triggered flip-flops can be identified by the triangle on th

50、e clock input.4.A D flip-flop is constructed by connecting an inverter between the Set and Clock terminals.第101页/共123页5.The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.6.Preset and Clear inputs are normally synchronous.7.When using maste