AllegroPCB数字信号完整性.pptx

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1、1About the AuthorJuergen FlammSenior Technical Sales LeaderCadence Design SystemsJuergen holds a MS EE degree from the“University Fridericiana”in Karlsruhe(Germany)Throughout his career,he has been actively involved at all levels and in all aspects of electronic design.He started designing wideband

2、telephony line amplifiers and repeaters at AEG Telefunken.Next he joined Litef(Litton Germany)as the lead engineer for sensor electronic development.He designed mixed mode analog/digital ASICs,miniaturized hybrid electronics and next level multi-board system in a box electronics.He relocated to the

3、United States in 1990 to join Litton corporate as the leader of an international technology transfer team.Shortly after,he was promoted to manager of the Analog Design Group to move on to manager of the Electronic Engineering Department.With the beginning of 2001,a planned careerr change brought Jue

4、rgen to Cadence.He joinedPSD as a Senior Technical Sales Leader with focus on the Allegro PCB SI family of tools.He holds 5 patents in the areas of performance electronics for fiber optic and MEMS sensors.第1页/共23页2AgendaIntroductionDescribing the problem Developing a SolutionStep1:Power delivery sys

5、tem analysis for a board using Allegro PCB PI Step2:Power delivery system analysis for a board/package combination using Allegro PCB SI SSN Step3:Combining Step1 and Step2 and moreSummaryQ&A第2页/共23页3IntroductionTodays high speed circuits,operating at fast edge rates(100MHz),combined with decreasing

6、supply voltage and increasing supply current demands,have been placing growing challenges on the design of power delivery systems.This presentation will show how Allegro PCB SI can be utilized to perform post-layout analysis of the power delivery system of a completed board design(see ICU 2003 paper

7、#2 for details).Post-layout analysis is only one use model of Allegro PCB SI.The tools real power will be experienced when also proactively employed for pre-layout design and analysis as well as for floor planning of a power delivery system.However,these use models are not subject of this presentati

8、on.第3页/共23页4Describing the ProblemExample:Parasitic elements in the PWR/GND supply path cause power supply noise and fluctuations on the chip supply rails第4页/共23页5Describing the Problem(cont.)Multiple elements must be considered simultaneously when analyzing a boards PWR/GND path from power source t

9、o the chip supply rails.Board power source(VRM)Output current slew rate capability,dynamic source impedance,Board plane structuresDifferential and common mode impedance,resonances,Board decoupling capacitorsType,quantity,pin escape and via connections,placement location,-Board traces and associated

10、viasInterconnecting PWR/GND planes and chip package pins,Package model(chip)Pins,traces,planes,vias,bond wires,第5页/共23页6Developing a solutionStep1Analyze a boards PWR/GND plane pairs impedance,including decoupling capacitors,using Allegro PCB PI frequency domain simulation.Step2Analyze the PWR/GND c

11、onnection path from planes to the chip power rails using Allegro PCB SI SSN time domain simulation.Step3Append Step2 model with Step1 source impedance model.Use appended model and Allegro PCB SI SSN simulation to evaluate PWR/GND bounce impact on signal waveform and timing.第6页/共23页7Step1Allegro PCB

12、PI Prepare board for and run Allegro PCB PI frequency domain simulationsComplete Allegro PCB SI“Setup Advisor”,focus on“Identify DC Nets”Complete Allegro PCB PI“Setup Wizard”,select at least 1 standard library capacitorUse“Report”to identify capacitor types per plane pairCreate/assign models for/to

13、identified capacitor typesUnder“Cap Libraries”in Board Folder and select used capacitor typesApproximate maximum worst case switching current,place noise source Determine VRM model parameters and place VRM Set preferences and run multi node simulationsAnalyze resulting impedance graphsOptionally det

14、ermine a simple worst case source impedance model(R,L,C)第7页/共23页8Step1Design&AnalysisReport Library Setup第8页/共23页9Step1Board with highlighted Plane Shapes,VRM,Noise Source,Grid Size 第9页/共23页10Step1 Multi Node Simulation resultSimple source impedance approximation:Z=40mOhm+j2pi*f*0.32nH第10页/共23页11Ste

15、p2Allegro PCB SI-SSNPrepare board for and run Allegro PCB SI SSN time domain simulationsUse Allegro PCB SI“Setup Advisor”,focus on“Device Setup”and“SI Model assignment”Check targeted device model for pin parasitic valuesAssign power bus to associated power pins of device modelAssign ground bus to as

16、sociated ground pins of device modelAssign power and ground bus to desired simultaneously switching I/O pins of device modelSelect preferences as intended and run Allegro PCB SI SSN simulation to create waveforms第11页/共23页12Step2Power&ground bus assignmentsPin dataA large package model instead of pin

17、 data could be used to provide a more comprehensive model.Device model preparation第12页/共23页13Step2 Power and ground bounce wave forms 第13页/共23页14Step2Additional signal waveform evaluation optionsExtract net into Allegro PCB SI 210(SigXp)tool,add current probe and perform reflection simulationEvaluat

18、e single net voltage and current waveformsHelpful to determine/validate rise/fall times and maximum switching current used in step1Set up and run EMI simulationEvaluate single net spectral current distributionHelpful to determine needed bandwidth for target impedance in step1第14页/共23页15Step2Extracte

19、d net with current probeDriver voltage wave formDriver current wave formSpectral current distribution第15页/共23页16Step3Allegro PCB SI SSN with added simple source impedance model parameters from Step1Use R and L model from Step1(slide 11)Divide R and L in half and add the values to each power and grou

20、nd pins parasitic values in the device model.Other optionsAdd to large package model parametersCombine Step1 and Step2 net lists 第16页/共23页17Step3 Comparison of Allegro PCB SI-SSN simulations with and without additional source impedance model added to pin parameters 第17页/共23页18Step3MorePerforming a c

21、omparison between Reflection and SSN simulation results.Evaluate power and ground bounce impact on a signals waveformEvaluate power and ground bounce impact on a signals timingEvaluate 第18页/共23页19Step3Reflection/SSN simulation comparisonFalling edge detail第19页/共23页20SummaryUsing Allegro PCB SI,we ha

22、ve briefly introduced options to perform post-layout analysis of a power delivery path from power source to the chip supply rails.We have used a three step approach utilizing Allegro PCB PI(SQ-PI)and Allegro PCB SI-SSN options and features of the tool.We have briefly touched on capabilities,which en

23、able the design engineer to perform comprehensive types of simulations.For example:Simulating the effect of power and ground bounce on signal waveform and timing.Knowing and intelligently utilizing the features and options of Allegro PCB SI can significantly increase a design engineers success.For example:Performing virtual prototyping,pre-layout analysis and floor planning of the power delivery system.第20页/共23页21Q&AContact information:Juergen FlammCell phone:818-642-2633Office phone:818-881-9965E-mail:第21页/共23页22第22页/共23页23感谢您的观看！第23页/共23页