AD8321在高速数据采集系统中的应用.pdf

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1、ADS s 21在高速数据采集系统中的应用-63一新 特 器 件 应 用AD8321在离速熬据来集系绕中沩宠用中国地质大学 夏益民 梁庆中 王广君 杜毓瑾Ap p Ii c a d o n o F AD8321h t h e Hi g h s p e e d Da t a Co l l e c o n s y s t e mi a 耐n Ii a l l g Qi 呷z h c l l l g Wa n g Gt】a【a 画u n Du i n摘要:AD821是AD公司生产的一种宽带宽、增益可数控的高频模拟信号调理芯片。文章介绍了AD821的功能特点、内部结构及基本连接 电路,给出了ADg 3

2、21芯片在 高速数据采集 系统中与MCS-51单片机的接口方法及应用程序。关键词:AD“21;高速数据采集系统;MCS-51单片机分类号:l Ng 11.7 文献标识码:B 文章编号:16-77(23)Os 63-O s1 引言在计算机测量、控制及信号处理中,数据采集起着十分重要的作罔。数据采集是获取信启、的一种重要手段。随着科学技术的发展,数据采集技术得到了越来越广泛的应用,同时人们对数据采集的各项技术指标:如采样频率、分辨率、输入范围等方面也提出了更高的要求,尤其是在采样频率和分辨率方面,更是成为设计者和使用者所共同关注的重要问题。于是,随着科技的进一步发展,高速和超高速数据采集系统应运而

3、生,并且取得了很大的发展。文中介绍了笔者设计的一个高速数据采集系统,它的原理图如图1所示。图 1中,高频模拟信号通过ADg s 21和可编程线性放大后,被输送到具有采样/保持功能的模数转换器中c 因为其采样频率为高频,所以在A/D后应接一个 肥血,以使得数据可以暂存在其中,然后再传送给计算机。信号调理模块的核心问题是如何确定放大增益。实际上,可以由计算机将所需放大的增益告钔单片机,然后由单片机再将控制字传送给AD“21最后再由信号调理模块输出合适的放大信号给数据采集模块。在高速数据采集系统中,现场输人信号是高频的模拟信号,它们的信号变化的范围都比较大,如果采用单一的增益放大,那么放大后的信号幅

4、值有可能超过A/D转换的量程,所以必须根据信号的变化来相应地调整放大器的增益。在 自动化程度较高的系统 中,可采用程序软件来控制放大器 的增益,AD8321正是这样一种具有增益可编程功能 的芯片。该芯片是美国AD公司生产的一种增益可编程的高频模拟信号调理芯片,可广泛应用于多种领域。AD821具有频带宽、噪声低、增益可编程且易于与单片机进行串行通信等优点,十分适合在数据采集系统做前置放大用。2 ADg 321简介笔者在设计中选用AD821是因为它具有两个显著优点:一是带宽高达 5MHz,可充分满足高频信号很宽的输人范围;二是增益可数控。此外,由于AD8321应用 s PI接 口技术与主控制器之间

5、进行通信,因此调试非常方便。2,1 AD8321的引脚功台 纟AD821采用DIP封装,其引脚排列见图2所示,其管脚描述如表1所列。2.2ADg s 21的内部结构及基本连接AD“21在前向模式下 由4个模拟功能模块组成,分别是衰减中心、数据锁存器、数据移位寄存器和放大器。其中,前向放大器可单端或多端输人,并可提供最大为1B的衰减。如果输人被用在不同的组态上,那么,输人信号必须180异相且为相同的幅信号调理模块 数据采集模块AD8321图1 高速数据采集系统原理图-64-舛电了无条件23年第5期 23年5月表1 AD8321管脚功能表脚 号代 号描 述1SDATA串行数据输人端CLK时钟输人端

6、DATEN使能端4,11,12,13,15,16GND公共参考地BYP1VCC/2参考 端6D低逻辑输人端7,8,9,17,20VCC公共正 电压源10VOUT信号输出端14BYP2内部旁管IN+正 向输人端VIN-反 向输人端度,这样才能确保适 当的增益精度和谐波性能。图3所示是 ADg s 21在 单端倒相模式下 的基本连接电路。另外,在 使用ADg s 21设计 电路时,一般还应当注意以下几点:(1)应给AD821提供优质(如低噪)的单”电源。尽管AD821在低于 卿 时也能运行,但是达不到最佳性能。(2)在ADg s 21的电源输人端应接-10u F的电容以便为低频信号退耦,而且应当用

7、5个 0.1u F退耦电容分别连在5个电源端(7,8,9,17,脚)上。同时,还应在管脚BYP1和BYP2上各连一个0,1u F的电容以为器件的内部接点去耦。所有的六个地端必须接到一个公共地上。2.3ADg s 21的极限参数 s 21的主要极限参数如下:电源电压 CC:+11;输人信号幅度:对于 IN-和IN+,其幅度为 0,5;而对 于SDATA、CLK、D龇N和PD,其幅度 范s DATACLKDATENGiBYP1围为-0,8+5.5;工作温度范围:们+g s;存储温度:b s +150。2,4AD8321的叩I接口在ADg s 21中,SPI是一个 同步串行通讯接口,它采用 三根信号

8、线 SDATA、EN和 CLK来传送数据及同步时钟,同时接收8位数据并通过使能线DA 来控制数据的输人以实现串行通信。它的输出增益由一个8比特字决定,其增益变化范围大于 o s。细B,增益变换为0,犭d B/s B。该通讯接 口每启动一次传送,主机都会产生一个时钟信号来作为同步时钟,这些数据以高有效位Mm 在前的方式,从SDA1端串行移人。其中,数据只有在信号线 DA孓EN为逻辑低时才能逐步移人,并在D州田N由低变高时进行增益转换,且每位数据只能在时钟的下降沿从单片机输人。图4是AD821的串行接口时序图。3 软件设计ADS321的增益 以0.%2刨B/Ls B为单位线性变化,增益 的计算公式

9、如下:当CODE7时,Av=2B-(71-CODE)0.7526d B)当CODE 127,Av=2甜B当128CODE199时,Av=2B+(199-CODE)0,7526d B)C5F O l u FC20,1u VCC CC CC CC c C BYP1 BYp 2SDATA G)D GWD G)D G下D G刂D图2 ADg 321DIP封装引脚 图图3 在单端倒相模式下的基本连接电路ADg s 21在高速数据采集系统中的应用-65-狃:式中,CODE是与存衅FAD叩叩 Sr l 罚A二IE二忄 衽EE亟EIII|硎匣数据锁存器中的8比特二进制字相|Tc|TWH默 耀扳璧1冠是单?c

10、川、丨 、l LNADg s 21应用SPI接口技术 与主 T:s|T裂瞽囵 黥忘。因此,其线路丽丽】GAI、TRANs FER(G2)GAIN TRANs FER(G1)g O51为代 表 的众 所 周知,以 图4串行接口 时序图 判断是否循环8次MCs-51系列单片机的功能强大,价 DJNz R1,L00P;MCS-51 (1:数据)格低廉,已在国内得到广泛应用。但因为系列单片机没有提供 SPI接 口,所以它与SH芯片的s Em P1,2;禁止新的数据输入,并将接口需要通过软件来实现。其模拟软件应具有以下锁存的数据送至衰减中心;以更新增益功能:(1)模拟串行时钟;m ;返回(2)8位数据串

11、行输出;4 结束语(3)片选控制。另外,还应通过软件对PD端置位或清零来允许或禁止信号从AD821输出。图5给出了g O51和 ADg 321的频带宽度高达 5MHz,可以充分满足在高速数据采集系统中输人信号的变化范围。同AD821之间的硬件接口。将g O51中R0寄存器 的8比特控制 字传送 到 时ADS s 21的 噪声低、线性好,放大后信号 的失真小。它利用SPI接口可以和任何单片机或微机进行ADg s 21的 程序如下:;允许ADB s 21有 输 出 通信,且无需外接元器件,因而可以方便地对增益进D而且它的体积小,连接线路简单,便于调MAIN:SETB P1.3;禁止数据从单片机传入

12、 行数控(SETB P1,2s PIOUN:M0 A,R0;将1B数据送 累加器Ac c 试。笔者在高速数 据采集 系统 中采用 以AD“21为0 核 b 的调理模块进行设计,收到了良好的效果。;使时钟输出为 参考文献CLR P1.1LCALL SPIOTI1.赵晓安,单 片机原理及应用。天津大学出版社,阿MP$为8 胃冤 东,赵 l 初.单 片微呸 垫 计算机原理与接口技#Og H;置循环次数片机传入 2陈光 ,1996 OTI:M0 R1,华中理工大学出版社CLR P1.2 ;允许数据从单 术。e v i c e s,In c,1999L00P N0P ;j 延时;左移 累加器Ac c 的

13、最高位至C 3AD:21曲棚h e e t,An d o g D|收稿日期:2t Xl 9-11-12C A、机输入槎 筝 讦 彐 鲆 亩 谔 寻:030525,c ;进位C送M0 P1,0 匚SDA线上1 ;使时钟输 出为1SETB P1。当199CODE255时,Av=Tl sNOP ;翅 时N0PCLR P1,1 ;时钟清零;在时钟下降沿将 1比 特数据送到从机(AD8321)N0PP1 0 SDATA8051P1 1 CLKAD8321P1 2 DATENP1 3PDGAI、TRANs FER(G2)图5 8051和 ADs 321之间的接口示意图N0PDATA SHIFT REGIS

14、TERGain Programmablea CATV Line Driver AD8321FEATURES FUNCTIONAL BLOCK DIAGRAM Linear in dB Gain Response Over 53 dB Range Drives Low Distortion 11 dBm Signal into 75 Load:VCC GND 53 dBc SFDR at 42 MHz APPLICATIONS Gain Programmable Line DriverHFC High Speed Data ModemsInteractive CATV Set-Top Boxes

15、CATV Plant Test EquipmentAD8321 POWER-DOWN/SWITCH INTER ATTENUATOR COREINV DATA SHIFT REGISTER DATA LATCH PWR AMP DATEN CLK REVERSE AMP SDATA General Purpose IF Variable Gain Block DESCRIPTION The AD8321 is packaged in a low cost 20-lead SOIC,operatesThe AD8321 is a low cost digitally controlled var

16、iable gain from a single+9 V supply,and has an operational temperatureamplifier optimized for coaxial line driving applications such as range of 40C to+85C.cable modems that are designed to the DOCSIS*(upstream)Very Low Output Noise Level Maintains Constant 75 Output Impedance Power-Up and Power-Dow

17、n Condition No Line Transformer Required VIN+Upper Bandwidth:235 MHz(Min Gain)VIN 9 V Single Supply Operation Power-Down Functionality Supports SPI Interface Low Cost VOUT PD standard.An 8-bit serial word determines the desired output gain over a 53.4 dB range,resulting in gain changes of 0.75 dB/LS

18、B.40 The AD8321 comprises a digitally controlled variable attenuator of 0 dB to 53.4 dB,which is preceded by a low noise,fixed 50 fO=VIN=(PIN=4137mV 15dB2MHz p-p m)(POUTMAX=11dGAIN)Bm HD3 HD2 gain buffer and followed by a low distortion high power amplifier.The AD8321 accepts a differential or singl

19、e-ended input signal.The output is specified for driving a 75 W load,such as coaxial cable,although the AD8321 is capable of driving other loads.Performance of 53 dBc is achieved with an output level up to 11 dBm at 42 MHz bandwidth using a 9 V supply.DISTORTION dBc60 70 A key performance and cost a

20、dvantage of the AD8321 results from the ability to maintain a constant 75 W output impedance during power-up and power-down conditions.This eliminates the need for external 75 W termination,resulting in twice the effective output voltage when compared to a standard operational amplifier,thus elimina

21、ting the need for a transformer.*Data-Over-Cable Service Interface Specifications REV.A Information furnished by Analog Devices is believed to be accurate and reliable.However,no responsibility is assumed by Analog Devices for its use,nor for any infringements of patents or other rights of third par

22、ties that may result from its use.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners.80 90 0 8 16 2432 4048 56 6472 GAIN CONTROL Decimal Figure 1.Harmonic Distortion vs

23、.Gain Control One Technology Way,P.O.Box 9106,Norwood,MA 02062-9106,U.S.A.Tel:781/329-4700 Fax:781/461-3113 2005 Analog Devices,Inc.All rights reserved.(VCC=+9 V,TA=+25C,VIN=0.137 V p-p,single-ended input,RL=75,RIN=AD8321SPECIFICATIONS 75 unless otherwise noted)Parameter Conditions Min Typ Max Unit

24、INPUT CHARACTERISTICS Specified AC Voltage Output=11 dBm,Max Gain 0.137 V p-p Noise Figure Max Gain,f=10 MHz 15 dB Input Resistance Single-Ended Input 820 W Differential Input 900 W Input Capacitance 2.0 pF GAIN CONTROL INTERFACE Gain Range 52.4 53.4 54.4 dB Maximum Gain 25.25 26 26.75 dB Minimum Ga

25、in 28.15 27.4 26.4 dB Gain Scaling Factor 0.7526 dB/LSB OUTPUT CHARACTERISTICS Bandwidth(3 dB)All Gain Codes 120 MHz Bandwidth Roll-Off f=65 MHz 0.8 dB Bandwidth Peaking f=65 MHz 0 dB Output Offset Voltage All Gain Codes,Full Temperature Range 30 mV Output Noise Spectral Density Max Gain,f=10 MHz 60

26、 nV/Hz Min Gain,f=10 MHz 20 nV/Hz Output Noise Temperature Sensitivity 0 TA +70C,Min Gain 0.02 nV/Hz/C Power-Down Spectral Density 1 nV/Hz 1 dB Compression Point Max Gain,f=10 MHz 19.5 dBm Output Impedance Power-Up and Power-Down 60 75 90 W OVERALL PERFORMANCE Worst Harmonic Distortion f=42 MHz,POUT

27、=11 dBm,VCC=+9 V 53 dBc f=65 MHz,POUT=11 dBm,VCC=+9 V 51 dBc Distortion Temperature Sensitivity 40C TA +85C 0.03 dBc/C Gain Accuracy f=10 MHz,All Gain Codes 0.2 dB Gain Temperature Sensitivity 0 TA +70C 0.004 dB/C Output Settling to 1 mV Gain Change TDATEN=1 Min to Max Gain,VIN=0 V 60 ns Input Chang

28、e Max Gain,VIN=0.15 V Step 30 ns Signal Feedthrough Power Down,65 MHz,Min Gain 80 dBc VIN=0.137 V p-p POWER CONTROL Power-Down Settling Time to 1 mV Max Gain,VIN=0 40 ns Power-Up Settling Time to 1 mV Max Gain,VIN=0 300 ns Power-Up/Down Pedestal Offset Max Gain,VIN=0 30 mV Power-Up/Down Glitch Max G

29、ain,VIN=0 40 mV p-p POWER SUPPLY Quiescent Current Power-Up,VCC=+9 V 82 90 97 mA Power-Down,VCC=+9 V 45 52 60 mA Specifications subject to change without notice.2 REV.A AD8321LOGIC INPUTS(TTL/CMOS Logic)(DATEN,CLK,SDATA,VCC=+9 V;Full Temperature Range)Parameter Min Typ Max Unit Logic“1”Voltage Logic

30、“0”Voltage Logic“1”Current(VINH=5 V)CLK,SDATA,DATEN Logic“0”Current(VINL=0 V)CLK,SDATA,DATEN Logic“1”Current(VINH=5 V)PD Logic“0”Current(VINL=0 V)PD 2.1 0 0 600 50 250 5.0 0.8 20 100 190 30 V V nA nA mA mA TIMING REQUIREMENTS(Full Temperature Range,VCC=+9 V,TR=TF=4 ns,fCLK=8 MHz unless otherwise not

31、ed.)Parameter Min Typ Max Unit Clock Pulsewidth(TWH)Clock Period(TC)Setup Time SDATA vs.Clock(TDS)Setup Time DATEN vs.Clock(TES)Hold Time SDATA vs.Clock(TDH)Hold Time DATEN vs.Clock(TEH)Input Rise and Fall Times,SDATA,DATEN,Clock(TR,TF)16.0 32.0 5.0 15.0 5.0 3.0 10 ns ns ns ns ns ns ns Specification

32、s subject to change without notice.TES VALID DATA WORD G1 MSB.LSB GAIN TRANSFER(G1)TDS TEH 8 CLOCK CYCLES GAIN TRANSFER(G2)TOFF TGS ANALOG OUTPUT SIGNAL AMPLITUDE(p-p)PD PEDESTAL CLK SDATA DATEN TON TC TWH VALID DATA WORD G2 Figure 2.Serial Interface Timing VALID DATA BIT MSB MSB-1 MSB-2 TDS TDH SDA

33、TA CLK Figure 3.SDATA Timing REV.A 3 AD8321 ABSOLUTE MAXIMUM RATINGS*PIN CONFIGURATION Supply Voltage+VS Pins 7,8,9,17,20 .+11 V Input Voltages SDATA Pins 18,19 .0.5 V CLK Pins 1,2,3,6.0.8 V to+5.5 V DATEN Internal Power Dissipation GND Small Outline(R).0.90 W BYP1 Operating Temperature Range .40C t

34、o+85C PD Storage Temperature Range .65C to+150C VCC Lead Temperature,Soldering 60 seconds .+300C VCC*Stresses above those listed under Absolute Maximum Ratings may cause perma-VCCnent damage to the device.This is a stress rating only;functional operation of thedevice at these or any other conditions

35、 above those indicated in the operational VOUTsection of this specification is not implied.Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.ORDERING GUIDE TOP VIEW(Not to Scale)20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 AD8321 GND GND VIN VCC B

36、YP2 GND GND VCC GND VIN+Model Temperature Range Package Description JA Package Option AD8321AR AD8321AR-REEL AD8321ARZ2 AD8321ARZ-REEL2 AD8321-EVAL 40C to+85C 40C to+85C 40C to+85C 40C to+85C 20-Lead SOIC 20-Lead SOIC 20-Lead SOIC 20-Lead SOIC Evaluation Board 58C/W1 58C/W1 58C/W1 58C/W1 R-20 R-20 R

37、-20 R-20 1Thermal Resistance measured on SEMI standard 4-layer board.2Z=Pb-free part.CAUTION ESD(electrostatic discharge)sensitive device.Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.Although the AD8321 features p

38、roprietary ESD protection circuitry,permanent damage may occur on devices subjected to high-energy electrostatic discharges.Therefore,proper ESD precautions are recommended to avoid performance degradation or loss of functionality.WARNING!ESD SENSITIVE DEVICE PIN FUNCTION DESCRIPTIONS Pin Function D

39、escription 1 SDATA Serial Data Input.This digital input allows for an 8-bit serial(gain)word to be loaded into the internal register with the MSB(most significant bit)first.2 CLK Clock Input.The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave register.A Logic 0

40、-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave.This requires the input serial data word to be valid at or before this clock transition.3 DATEN Data Enable Low Input.This port controls the 8-bit parallel data latch and shift register.A Logic 0-to1 transition tr

41、ansfers the latched data to the attenuator core(updates the gain)and simultaneously inhibits serial data transfer into the register.A 1-to-0 transition inhibits the data latch(holds the previous gain state)and simultaneously enables the register for serial data load.4,11,12,13,15,16 GND Common Exter

42、nal Ground Reference.5 BYP1 VCC/2 Reference Pin.A dc output reference level that is equal to 1/2 of the supply voltage(VCC).This port should be externally ac-decoupled(0.1 mF capacitor).For external use of this reference voltage,buffering is required.6 PD Power-Down Low Logic Input.A Logic 0 powers

43、down(shuts off)the power amplifier disabling the output signal and enabling the reverse amplifier.A Logic 1 enables the output power amplifier and disables the reverse amplifier.7,8,9,17,20 VCC Common Positive External Supply Voltage.10 VOUT Output Signal Port.DC-biased to approximately VCC/2.14 BYP

44、2 Internal Bypass.This pin must be externally ac-decoupled(0.1 mF capacitor).18 VIN+Noninverting Input.DC-biased to approximately VCC/2.For single-ended inverting operation,use 0.1 mF decoupling capacitor between VIN+and ground.19 VIN Inverting Input.DC-biased to approximately VCC/2.Should be ac-cou

45、pled with a 0.1 mF capacitor.4 REV.A 0 0.3 0.6 70 Typical Performance CharacteristicsAD8321 f=65MHz f=10MHz f=42MHz7030 20 60 OUTPUT NOISE nV/Hz10 46D 23D 00D 71D 50 40 30 20 10 f=10MHz PD=1 GAIN ERROR dB POUT dBmGAIN dB0 10 0.3 0.6 20 0.9 30 401.2 0 8 1624324048566472 0.1 1 10 100 1000 0 8 16243240

46、48566472 GAIN CONTROL Decimal FREQUENCY MHzGAIN CONTROL Decimal Figure 4.Gain Error vs.Gain Control Figure 5.AC ResponseFigure 6.Output Referred Noise vs.Gain Control 30 47 PD=1 MAX GAIN(71D)MIN GAIN(00D)10 fO=65MHz VIN=0.137V p-p(PIN=15dBm)(POUT=11dBm MAX GAIN)HD3 HD2 5980 1 10 100 0 8 162432404856

47、6472 5 15 25 35 45 55 65 PIN=(POUTMAX14dBm =12dB GAIN)m PIN=(POUMAX 15dBT=11dBm GAIN)m PIN=(POUTMAX13dBm =13dB GAIN)m PIN=(POUMAX 17dBT=9dBm GAIN)m 60 40 OUTPUT NOISE nV/Hz50 DISTORTION dBcDISTORTION dBc50 50 40 53 60 30 56 7020 FREQUENCY MHzGAIN CONTROL Decimal FUNDAMENTAL FREQUENCY MHz Figure 7.Ou

48、tput Referred Noise vs.Figure 8.Harmonic Distortion vs.Figure 9.Second Order Harmonic Frequency Gain Control Distortion vs.Frequency for Various Input Levels 20 3047 59 80 POUT=11dBm MAX GAIN 22 PIN=(POUTMAX 13dB=13dBGAIN)m m PIN=14dBm(POUT=MAX G 12dBmAIN)PIN=(POUMAX T 15dBGAIN)=11dBm m PIN=(POUMAX

49、17dBT=9dBm GAIN)m POUT=11dBm MAX GAIN293RD ORDER INTERCEPT dBm0 50 28 27DISTORTION dBc20 2653 40 25 2456 60 23 5 15 25 35 45 55 65 41.0 41.4 41.8 42.2 42.6 43.0 5 15 25 35 45 55 65 FUNDAMENTAL FREQUENCY MHz FREQUENCY MHzFREQUENCY MHz Figure 10.Third Order Harmonic Figure 11.Two-Tone Intermodula-Figu

50、re 12.Third Order Intercept vs.Distortion vs.Frequency for Various tion Distortion Frequency Input Levels REV.A5 AD832134 30 FREQUENCY MHz 1 10 100 CL=10pF CL=0pF CL=20pF CL=50pF MAX GAIN POUT=11dBm GAIN dB26 22 18 14 5V 75ns MAX GAIN VIN=0V p-p 15mV PD VOUT 5V 75ns MIN GAIN VIN=0V p-p 5mV PD VOUT F