74HC595中文资料,74HC595D规格书,74HC595N技术文档,DAT.pdf
《74HC595中文资料,74HC595D规格书,74HC595N技术文档,DAT.pdf》由会员分享,可在线阅读,更多相关《74HC595中文资料,74HC595D规格书,74HC595N技术文档,DAT.pdf(28页珍藏版)》请在淘文阁 - 分享文档赚钱的网站上搜索。
1、DATA SHEETDATA SHEETProduct specificationSupersedes data of 1998 Jun 042003 Jun 25INTEGRATED CIRCUITS74HC595;74HCT5958-bit serial-in,serial or parallel-outshift register with output latches;3-state2003 Jun 252Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregi
2、ster with output latches;3-state74HC595;74HCT595FEATURES 8-bit serial input 8-bit serial or parallel output Storage register with 3-state outputs Shift register with direct clear 100 MHz(typical)shift out frequency ESD protection:HBM EIA/JESD22-A114-A exceeds 2000 VMM EIA/JESD22-A115-A exceeds 200 V
3、.APPLICATIONS Serial-to-parallel data conversion Remote control holding register.DESCRIPTIONThe74HC/HCT595arehigh-speedSi-gateCMOSdevicesand are pin compatible with low power Schottky TTL(LSTTL).They are specified in compliance with JEDECstandard no.7A.The 74HC/HCT595 is an 8-stage serial shift regi
4、ster with astorage register and 3-state outputs.The shift register andstorage register have separate clocks.Data is shifted on the positive-going transitions of theSH_CP input.The data in each register is transferred tothe storage register on a positive-going transition of theST_CP input.If both clo
5、cks are connected together,theshift register will always be one clock pulse ahead of thestorage register.The shift register has a serial input(DS)and a serialstandard output(Q7)for cascading.It is also providedwith asynchronous reset(active LOW)for all 8 shiftregister stages.The storage register has
6、 8 parallel 3-statebus driver outputs.Data in the storage register appears atthe output whenever the output enable input(OE)is LOW.QUICK REFERENCE DATAGND=0 V;Tamb=25 C;tr=tf=6 ns.Notes1.CPD is used to determine the dynamic power dissipation(PDin W).PD=CPD VCC2 fi N+(CL VCC2 fo)where:fi=input freque
7、ncy in MHz;fo=output frequency in MHz;CL=output load capacitance in pF;VCC=supply voltage in Volts;N=total load switching outputs;(CL VCC2 fo)=sum of the outputs.2.For 74HC595 the condition is VI=GND to VCC.For 74HCT595 the condition is VI=GND to VCC 1.5 V.SYMBOLPARAMETERCONDITIONSTYPICALUNIT74HC74H
8、CTtPHL/tPLHpropagation delayCL=50 pF;VCC=4.5 VSH_CP to Q71925nsSH_CP to Qn2024nsMR to Q710052nsfmaxmaximum clock frequency SH_CP and ST_CP10057MHzCIinput capacitance3.53.5pFCPDpower dissipation capacitance per packagenotes 1 and 2115130pF深圳市万瑞尔科技有限公司,NXP代理商,WWW.WONREAL.NET 0755-282697892003 Jun 253P
9、hilips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595FUNCTION TABLESee note 1.Note1.H=HIGH voltage level;L=LOW voltage level;=LOW-to-HIGH transition;=HIGH-to-LOW transition;Z=high-impedance OFF-state;n.c.=no change;
10、X=dont care.ORDERING INFORMATIONINPUTOUTPUTFUNCTIONSH_CPST_CPOEMRDSQ7QnXXLLXLn.c.a LOW level on MR only affects the shift registersXLLXLLempty shift register loaded into storage registerXXHLXLZshift register clear;parallel outputs in high-impedanceOFF-stateXLHHQ6n.c.logic high level shifted into shi
11、ft register stage 0;contents of all shift register stages shifted through,e.g.previous state of stage 6(internal Q6)appears on theserial output(Q7)XLHXn.c.Qncontents of shift register stages(internal Qn)aretransferred to the storage register and parallel outputstagesLHXQ6Qncontents of shift register
12、 shifted through;previouscontents of the shift register is transferred to thestorage register and the parallel output stagesTYPE NUMBERPACKAGETEMPERATURERANGEPINSPACKAGEMATERIALCODE74HC595N40 to+125 C16DIP16plasticSOT38-474HCT595N40 to+125 C16DIP16plasticSOT38-474HC595D40 to+125 C16SO16plasticSOT109
13、-174HCT595D40 to+125 C16SO16plasticSOT109-174HC595DB40 to+125 C16SSOP16plasticSOT338-174HCT595DB40 to+125 C16SSOP16plasticSOT338-174HC595PW40 to+125 C16TSSOP16plasticSOT403-174HCT595PW40 to+125 C16TSSOP16plasticSOT403-174HC595BQ40 to+125 C16DHVQFN16plasticSOT763-174HCT595BQ40 to+125 C16DHVQFN16plast
14、icSOT763-12003 Jun 254Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595PINNINGPINSYMBOLDESCRIPTION1Q1parallel data output2Q2parallel data output3Q3parallel data output4Q4parallel data output5Q5parallel data out
15、put6Q6parallel data output7Q7parallel data output8GNDground(0 V)9Q7serial data output10MRmaster reset(active LOW)11SH_CPshift register clock input12ST_CPstorage register clock input13OEoutput enable(active LOW)14DSserial data input15Q0parallel data output16VCCpositive supply voltagehandbook,halfpage
16、Q1Q2Q3Q4Q5Q6Q7Q7Q0DSGNDST_CPSH_CPVCCOE12345678161514131211109595MLA001MRFig.1Pin configuration DIP16,SO16 and(T)SSOP16.handbook,halfpage116GND(1)Q1VCC823457Q2Q3Q4Q5Q615141312106119GNDTop viewMBL893Q7Q7MRSH_CPST_CPOEDSQ0Fig.2 Pin configuration DHVQFN16.(1)The die substrate is attached to this pad usi
17、ng conductive dieattach material.It can not be used as a supply pin or input.2003 Jun 255Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595handbook,halfpageOEMR91512345671310141112MLA002Q1Q0Q2Q3Q4Q5Q6Q7Q7DSST_CP
18、SH_CPFig.3 Logic symbol.handbook,halfpageMSA69815912345671D2DC1/101114C21213EN3SRG8R3OEMRQ1Q0Q2Q3Q4Q5Q6Q7Q7DSST_CPSH_CPFig.4 IEC logic symbol.handbook,full pagewidthST_CPDSSH_CPMRQ78-STAGE SHIFT REGISTER8-BIT STORAGE REGISTER141110129OE3-STATE OUTPUTSQ1Q2Q3Q5Q6Q7Q4Q015123456713MLA003Fig.5 Functional
19、 diagram.2003 Jun 256Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595handbook,full pagewidthSTAGE 0STAGES 1 to 6STAGE 7FF0DCPQRLATCHDCPQFF7DCPQRLATCHDCPQMLA010DQQ1Q2Q3Q4Q5Q6Q7Q7Q0DSST_CPSH_CPOEMRFig.6 Logic di
20、agram.2003 Jun 257Philips SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595handbook,full pagewidthhigh-impedance OFF-stateST_CPDSSH_CPMROEQ1Q0Q7Q6Q7MLA005-1Fig.6 Timing diagram.2003 Jun 258Philips SemiconductorsProduct
21、 specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595RECOMMENDED OPERATING CONDITIONSLIMITED VALUESIn accordance with the Absolute Maximum Rating System(IEC 60134);voltages are referenced to GND(ground=0 V).Note1.For DIP16 packages:above 70 C
22、derate linearly with 12 mW/K.For SO16 packages:above 70 C derate linearly with 8 mW/K.For SSOP16 packages:above 60 C derate linearly with 5.5 mW/K.For TSSOP16 packages:above 60 C derate linearly with 5.5 mW/K.For DHVQFN16 packages:above 60 C derate linearly with 4.5 mW/K.SYMBOLPARAMETERCONDITIONS74H
23、C74HCTUNITMIN.TYP.MAX.MIN.TYP.MAX.VCCsupply voltage2.05.06.04.55.05.5VVIinput voltage0VCC0VCCVVOoutput voltage0VCC0VCCVTambambient temperature40+12540+125Ctr,tfinput rise and fall timeVCC=2.0 V1000nsVCC=4.5 V6.05006.0500nsVCC=6.0 V400nsSYMBOLPARAMETERCONDITIONSMIN.MAX.UNITVCCsupply voltage0.5+7.0VII
24、Kinput diode currentVI VCC+0.5 V20mAIOKoutput diode currentVO VCC+0.5 V20mAIOoutput source or sink currentVO=0.5 V to VCC+0.5 VQ7 standard output25mAQn bus driver outputs35mAICC,IGNDVCC or GND current70mATstgstorage temperature65+150CPtotpower dissipationTamb=40 to+125 C;note 1500mW2003 Jun 259Phili
25、ps SemiconductorsProduct specification8-bit serial-in,serial or parallel-out shiftregister with output latches;3-state74HC595;74HCT595DC CHARACTERISTICSType 74HCAt recommended operating conditions;voltages are referenced to GND(ground=0 V).SYMBOLPARAMETERTEST CONDITIONSMIN.TYP.MAX.UNITOTHERVCC(V)Tam
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 74 HC595 中文 资料 HC595D 规格书 HC595N 技术 文档 DAT
限制150内