JN516X芯片规格书.pdf

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1、 Data Sheet:JN516x IEEE802.15.4 Wireless Microcontroller NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 1 Overview Features:Radio 2.4GHz IEEE802.15.4 compliant 128-bit AES security processor MAC accelerator with packet formatting,CRCs,address check,auto-acks,timers Integrated ultra low power

2、sleep oscillator 0.6A 2.0V to 3.6V battery operation Deep sleep current 0.12A(Wake-up from IO)=D QRise=10mS 1.44 1.41 V Rising Falling Spike Rejection Square wave pulse 1us Triangular wave pulse 10us 1.2 1.3 V Depth of pulse to trigger reset Reset stabilisation time(tSTAB)180 s Note 1 Chip current w

3、hen held in reset (IRESET)6 uA Brown-Out Reset Current Consumption 80 nA Supply Voltage Monitor Threshold Voltage(VTH)1.86 1.92 2.02 2.11 2.21 2.30 2.59 2.88 1.94 2.00 2.10 2.20 2.30 2.40 2.70 3.00 2.00 2.06 2.16 2.27 2.37 2.47 2.78 3.09 V Configurable threshold with 8 levels Supply Voltage Monitor

4、Hysteresis(VHYS)37 38 45 52 58 65 82 100 mV Corresponding to the 8 threshold levels 1 Time from release of reset to start of executing of bootloader code from internal flash.An extra 15us is incurred if the BOR circuit has been activated(e.g.,if the supply voltage has been ramped up from 0V).NXP Lab

5、oratories UK 2013 JN-DS-JN516x v1.3 Production 63 VTH+VHYSVTHDVDDInternal BORestInternal SVM VPOTFigure 41 Brown-out Reset Followed By Supply Voltage Montior trigger 19.3.2 SPI Master Timing tSSHtSSStCKtSItHIMOSI(mode=1,3)SSMOSI(mode=0,2)MISO(mode=0,2)MISO(mode=1,3)tVOtVOCLK(mode=0,1)tSItHICLK(mode=

6、2,3)Figure 42:SPI Master Timing Parameter Symbol Min Max Unit Clock period tCK 62.5-ns Data setup time tSI 16.7 3.3V 18.2 2.7V 21.0 2.0V-ns Data hold time tHI 0 ns Data invalid period tVO-15 ns Select set-up period tSSS 60-ns Select hold period tSSH 30(SPICLK=16MHz)0(SPICLK16MHz,mode=0 or 2)60(SPICL

7、K16MHz,mode=1 or 3)-ns 64 JN-DS-JN516x v1.3 Production NXP Laboratories UK 2013 19.3.3 SPI Slave Timing Parameter Symbol Min Max Unit Clock period tCK 125-ns Idle time tIDLE 125-ns Data input setup time tSI 10-ns Data input hold time tHI 10-ns Data output invalid period from SPISCLK falling edge tCK

8、VO-30 ns Data output invalid period from SPISSEL falling edge tSELVO 30 ns Delay from SPISSEL falling edge to SPISCLK rising edge tSELA 30-ns Delay from SPISCLK falling edge to SPISSEL rising edge tSELN 30-ns SPISCLK SPISSEL SPISMOSI SPISMISO tIDLE tSELN tSI tHI tSELA tCK tCKVO tSELVO Figure 43:SPI

9、Slave Timing NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 65 19.3.4 Two-wire Serial Interface tBUFSrPSStLOWtHD;STAtFtRtHD;DATtHIGHtSU;DATtSU;STAtHD;STAtSU;STOtSPtRtFSIF_DSIF_CLK Figure 44:Two-wire Serial Interface Timing Parameter Symbol Standard Mode Fast Mode Unit Min Max Min Max SIF_CLK

10、clock frequency fSCL 0 100 0 400 kHz Hold time(repeated)START condition.After this period,the first clock pulse is generated tHD:STA 4-0.6-s LOW period of the SIF_CLK clock tLOW 4.7-1.3-s HIGH period of the SIF_CLK clock tHIGH 4-0.6-s Set-up time for repeated START condition tSU:STA 4.7-0.6-s Data s

11、etup time SIF_D tSU:DAT 0.25-0.1-s Rise Time SIF_D and SIF_CLK tR-1000 20+0.1Cb 300 ns Fall Time SIF_D and SIF_CLK tF-300 20+0.1Cb 300 ns Set-up time for STOP condition tSU:STO 4-0.6-s Bus free time between a STOP and START condition tBUF 4.7-1.3-s Pulse width of spikes that will be suppressed by in

12、put filters(Note 1)tSP-60-60 ns Capacitive load for each bus line Cb-400-400 pF Noise margin at the LOW level for each connected device(including hysteresis)Vnl 0.1VDD-0.1VDD-V Noise margin at the HIGH level for each connected device(including hysteresis)Vnh 0.2VDD-0.2VDD-V Note 1:This figure indica

13、tes the pulse width that is guaranteed to be suppressed.Pulse with widths up to 125nsec may also get suppressed.19.3.5 Wakeup Timings Parameter Min Typ Max Unit Notes Time for crystal to stabilise ready to run CPU 0.74 ms Reached oscillator amplitude threshold.Default bias current Time for crystal t

14、o stabilise ready for radio activity 1.0 ms Wake up from Deep Sleep or from Sleep 170 s Time to CPU release Start-up time from reset RESETN pin,BOR or SVM 180 s Time to CPU release Wake up from CPU Doze mode 0.2 s 66 JN-DS-JN516x v1.3 Production NXP Laboratories UK 2013 19.3.6 Bandgap Reference VDD=

15、2.0 to 3.6V,-40 to+125C,italic+85 C Bold+125 C Parameter Min Typ Max Unit Notes Voltage 1.198 1.235 1.260 V DC power supply rejection 58 dB at 25C Temperature coefficient +40+135+65+93 ppm/C 20 to 85C-40C to 20C 20 to 125 C-40C to 85C Point of inflexion+80 C 19.3.7 Analogue to Digital Converters VDD

16、=3.0V,VREF=1.2V,-40 to+125C,italic+85 C Bold+125 C Parameter Min Typ Max Unit Notes Resolution 10 bits 500kHz Clock Current consumption 550 A Integral nonlinearity 1.6,1.8 LSB Differential nonlinearity-0.5 +0.5 LSB Guaranteed monotonic Offset error -10-20 mV 0 to Vref range 0 to 2Vref range Gain err

17、or +10+20 mV 0 to Vref range 0 to 2Vref range Internal clock 0.25,0.5 or 1.0 MHz 16MHz input clock,16,32or 64 No.internal clock periods to sample input 2,4,6 or 8 Programmable Conversion time 9.5 148 s Programmable Input voltage range 0.04 Vref or 2*Vref V Switchable.Refer to 17.1.1 Vref(Internal)Se

18、e Section 19.3.6 Vref(External)1.15 1.2 1.6 V Allowable range into VREF pin Input capacitance 8 pF In series with 5K ohms NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 67 19.3.8 Comparator VDD=2.0 to 3.6V-40 to+125C,italic+85 C Bold+125 C Parameter Min Typ Max Unit Notes Analogue response ti

19、me(normal)90 125,130 ns+/-250mV overdrive 10pF load Total response time(normal)including delay to Interrupt controller 125 +125,130 ns Digital delay can be up to a max.of two 16MHz clock periods Analogue response time(low power)2.2 2.8 s+/-250mV overdrive No digital delay Hysteresis 7 14 28 10 20 40

20、 16,17 28,30 53,57 mV Programmable in 3 steps and zero Vref(Internal)See Section 19.3.6 V Common Mode input range 0 Vdd V Current(normal mode)56 73 96,100 A Current(low power mode)0.8 1.0,1.1 A 19.3.9 32kHz RC Oscillator VDD=2.0 to 3.6V,-40 to+125 C,italic+85 C Bold+125 C Parameter Min Typ Max Unit

21、Notes Current consumption of cell and counter logic(default)590 520 465 720,800 660,740 600,650 nA 3.6V 3.0V 2.0V Current consumption of cell and counter logic(low power)465 375 290 500,550 425,460 330,370 nA 3.6V 3.0V 2.0V 32kHz clock un-calibrated accuracy -10%32kHz+40%Without temperature&voltage

22、variation(note1)Calibrated 32kHz accuracy(default)Low power 300 600 ppm For a 1 second sleep period calibrating over 20 x 32kHz clock periods Variation with temperature -0.010-0.020%/C Default Low power Variation with VDD2 -3.0%/V Note1:Measured at 3v and 25 deg C 68 JN-DS-JN516x v1.3 Production NXP

23、 Laboratories UK 2013 19.3.10 32kHz Crystal Oscillator VDD=2.0 to 3.6V,-40 to+125C,italic+85 C Bold+125 C Parameter Min Typ Max Unit Notes Current consumption of cell and counter logic 1.4 1.75,2.0 A This is sensitive to the ESR of the crystal,Vdd and total capacitance at each pin Start up time 0.6

24、s Assuming xtal with ESR of less than 40kohms and CL=9pF External caps=15pF(Vdd/2mV pk-pk)see Appendix B Input capacitance 1.4 pF Bondpad and package Transconductance 18.5 A/V External Capacitors (CL=9pF)15 pF Total external capacitance needs to be 2*CL,allowing for stray capacitance from chip,packa

25、ge and PCB Amplitude at Xout Vdd-0.2 Vp-p 19.3.11 32MHz Crystal Oscillator VDD=2.0 to 3.6V,-40 to+125C,italic+85 C Bold+125 C Parameter Min Typ Max Unit Notes Current consumption 300 375 450,500 A Excluding bandgap ref.Start up time 0.74 ms Assuming xtal with ESR of less than 40ohms and CL=9pF Exter

26、nal caps=15pF see Appendix B Input capacitance 1.4 pF Bondpad and package Transconductance 3.65,3.55 4.30 5.16 mA/V DC voltages,XTALIN/XTALOUT 390/432 375/412 425/472 470/527 mV External Capacitors (CL=9pF)15 pF Total external capacitance needs to be 2*CL,allowing for stray capacitance from chip,pac

27、kage and PCB Amplitude detect threshold 320 mVp-p Threshold detection accessible via API NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 69 19.3.12 High-Speed RC Oscillator VDD=2.0 to 3.6V,-40 to+125C,italic+85 C Bold+125 C Parameter Min Typ Max Unit Notes Current consumption of cell 81 145 25

28、0,275 A Clock native accuracy-16%+18%Un-calibrated frequency 26.1 MHz Calibrated centre frequency accuracy-1.6%32.1 +1.6%MHz Without temperature&voltage variation Calibrated centre frequency accuracy-4%32.1 +5%MHz Including temperature&voltage variation Variation with temperature-0.024,-0.015 +0.009

29、,+0.006%/C Variation with VDD2-0.25+0.25+0.5,+0.6%/V Startup time 2.4 us 19.3.13 Temperature Sensor VDD=2.0 to 3.6V,-40 to+125C,italic+85 C Bold+125 C Parameter Min Typ Max Unit Notes Operating Range-40-125 C Sensor Gain-1.56-1.66-1.76 mV/C Accuracy-7 C Non-linearity-2.0,3.0 C Output Voltage 610,540

30、 840 mV Includes absolute variation due to manufacturing&temp Typical Voltage 730 mV Typical at 3.0V 25C Resolution 0.666 0.706 0.751 C/LSB 0 to Vref ADC I/P Range 19.3.14 Non-Volatile Memory VDD=2.0 to 3.6V,-40 to+125C,italic+85 C Bold+125 C Parameter Min Typ Max Unit Notes Flash endurance 10K 100/

31、50K Cycle Program/erase Flash erase time 100 ms One or more sectors Flash programming time 1.0 ms 256 bytes EEPROM endurance 100K 1M/500K C Program/erase(see 4.4)EEPROM erase time 1.8 ms One 64 bytes page EEPROM programming time 1.1 ms Between 1&64 bytes Retention time powered unpowered 10 20 Years

32、Flash&EEPROM 70 JN-DS-JN516x v1.3 Production NXP Laboratories UK 2013 19.3.15 Radio Transceiver This JN516x meets all the requirements of the IEEE802.15.4 standard over 2.0-3.6V and offers the following improved RF characteristics.All RF characteristics are measured single ended.This part also meets

33、 the following regulatory body approvals,when used with NXPs Module Reference Designs.Compliant with FCC part 15,rules,IC Canada,ETSI ETS 300-328 and Japan ARIB STD-T66 The PCB schematic and layout rules detailed in Appendix B.4 must be followed.Failure to do so will likely result in the JN516x fail

34、ing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application.Parameter Min Typical Max Notes RF Port Characteristics Type Single Ended Impedance 1 50ohm 2.4-2.5GHz Frequency range 2.400 GHz 2.485GHz ESD levels(pin 17)2KV(HBM)500

35、v(CDM)1)With external matching inductors and assuming PCB layout as in Appendix B.4.NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Production 71 Radio Parameters:2.0-3.6V,+25C Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity-92-95 dBm Nominal for 1%PER,as per 802.15.4 Se

36、ction 6.5.3.3 Maximum input signal +10 dBm For 1%PER,measured as sensitivity Adjacent channel rejection(-1/+1 ch)CW Interferer 19/34 27/49 dBc For 1%PER,with wanted signal 3dB,above sensitivity.(Note1,2)(modulated interferer)Alternate channel rejection(-2/+2 ch)CW Interferer 40/44 54/54 dBc For 1%PE

37、R,with wanted signal 3dB,above sensitivity.(Note1,2)(modulated interferer)Other in band rejection 2.4 to 2.4835 GHz,excluding adj channels 48 dBc For 1%PER with wanted signal 3dB above sensitivity.(Note1)Out of band rejection 52 dBc For 1%PER with wanted signal 3dB above sensitivity.All frequencies

38、except wanted/2 which is 8dB lower.(Note1)Spurious emissions(RX)-65 -70-60 dBm Measured conducted into 50ohms 30MHz to 1GHz 1GHz to 12GHz Intermodulation protection 40 dB For 1%PER at with wanted signal 3dB above sensitivity.Modulated Interferers at 2&4 channel separation(Note1)RSSI linearity-4 +4 d

39、B-95 to-10dBm.Available through Hardware API Transmitter Characteristics Transmit power+0.5+2.5 dBm Output power control range -35 dB In three 12dB steps (Note3)Spurious emissions(TX)-40 -70 -70 dBm Measured conducted into 50ohms 30MHz to 1GHz,1GHz to12.5GHz,The following exceptions apply 1.8 to 1.9

40、GHz&5.15 to 5.3GHz EVM Offset 3.0 4.5%At maximum output power Transmit Power Spectral Density -38-20 dBc At greater than 3.5MHz offset,as per 802.15.4,Section 6.5.3.1 72 JN-DS-JN516x v1.3 Production NXP Laboratories UK 2013 Radio Parameters:2.0-3.6V,-40C Parameter Min Typical Max Unit Notes Receiver

41、 Characteristics Receive sensitivity-93.0-96.0 dBm Nominal for 1%PER,as per 802.15.4 Section 6.5.3.3 Maximum input signal +10 dBm For 1%PER,measured as sensitivity Adjacent channel rejection(-1/+1 ch)CW Interferer 19/34 TBC dBc For 1%PER,with wanted signal 3dB,above sensitivity.(Note1,2)(modulated i

42、nterferer)Alternate channel rejection(-2/+2 ch)CW Interferer 40/44 TBC dBc For 1%PER,with wanted signal 3dB,above sensitivity.(Note1,2)(modulated interferer)Other in band rejection 2.4 to 2.4835 GHz,excluding adj channels 47 dBc For 1%PER with wanted signal 3dB above sensitivity.(Note1)Out of band r

43、ejection 49 dBc For 1%PER with wanted signal 3dB above sensitivity.All frequencies except wanted/2 which is 8dB lower.(Note1)Spurious emissions(RX)-64 -70-60 dBm Measured conducted into 50ohms 30MHz to 1GHz 1GHz to 12GHz Intermodulation protection 39 dB For 1%PER at with wanted signal 3dB above sens

44、itivity.Modulated Interferers at 2&4 channel separation(Note1)RSSI linearity-4 +4 dB-95 to-10dBm.Available through Hardware API Transmitter Characteristics Transmit power 0+2.00 dBm Output power control range -35 dB In three 12dB steps (Note3)Spurious emissions(TX)-40 -70 -70 dBm Measured conducted

45、into 50ohms 30MHz to 1GHz,1GHz to12.5GHz,The following exceptions apply 1.8 to 1.9GHz&5.15 to 5.3GHz EVM Offset 3.0 4.5%At maximum output power Transmit Power Spectral Density -38-20 dBc At greater than 3.5MHz offset,as per 802.15.4,Section 6.5.3.1 NXP Laboratories UK 2013 JN-DS-JN516x v1.3 Producti

46、on 73 Radio Parameters:2.0-3.6V,+85C Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity-90-93 dBm Nominal for 1%PER,as per 802.15.4 Section 6.5.3.3 Maximum input signal +10 dBm For 1%PER,measured as sensitivity Adjacent channel rejection(-1/+1 ch)CW Interferer 19/34 TB

47、C dBc For 1%PER,with wanted signal 3dB,above sensitivity.(Note1,2)(modulated interferer)Alternate channel rejection(-2/+2 ch)CW Interferer 40/44 TBC dBc For 1%PER,with wanted signal 3dB,above sensitivity.(Note1,2)(modulated interferer)Other in band rejection 2.4 to 2.4835 GHz,excluding adj channels

48、49 dBc For 1%PER with wanted signal 3dB above sensitivity.(Note1)Out of band rejection 53 dBc For 1%PER with wanted signal 3dB above sensitivity.All frequencies except wanted/2 which is 8dB lower.(Note1)Spurious emissions(RX)-66 -70-61 dBm Measured conducted into 50ohms 30MHz to 1GHz 1GHz to 12GHz I

49、ntermodulation protection 41 dB For 1%PER at with wanted signal 3dB above sensitivity.Modulated Interferers at 2&4 channel separation(Note1)RSSI linearity-4 +4 dB-95 to-10dBm.Available through Hardware API Transmitter Characteristics Transmit power 0+2.0 dBm Output power control range -35 dB In thre

50、e 12dB steps (Note3)Spurious emissions(TX)-40 -70 -70 dBm Measured conducted into 50ohms 30MHz to 1GHz,1GHz to12.5GHz,The following exceptions apply 1.8 to 1.9GHz&5.15 to 5.3GHz EVM Offset 3.0 4.5%At maximum output power Transmit Power Spectral Density -38-20 dBc At greater than 3.5MHz offset,as per