计算机组成原理计算题设计题.doc

《计算机组成原理计算题设计题.doc》由会员分享，可在线阅读，更多相关《计算机组成原理计算题设计题.doc（7页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、. -1. IEEE 754 format of X is (41360000)16, what is its decimal value?将十六进制数展开，可得二进制数格式为：0 100 0001 0 011 0110 0000 0000 0000 0000指数e=阶码127=1000001001111111= 00000011 =310包括隐藏位1的尾数1.M = 1.011 0110 0000 0000 0000 0000 = 1.011011于是有：X = (-1)s * 1.M * 2e = +(1.011011)2 * 23 = + (1011.011)2 = (11.375)10

2、2.Let the carry bits of an adder are C4, C3, C2, C1. C0 is the carry from the low bit. Please give the logic expressions of C4, C3, C2, C1 in ripple carry mode and carry look ahead mode respectively.(1)串行进位G1 = A1B1 , P1 = A1 B1G2 = A2B2 , P2 = A2 B2G3 = A3B3 , P3 = A3 B3G4 = A4B4 , P4 = A4 B4C1 = G

3、1 + P1P0C2 = G2 + P2C1C3 = G3 + P3C2C4 = G4 +P4C3(2)并行进位C1 = G1 + P1C0C2 = G2 + P2G1 + P2P1C0C3 = G3 + P3G2 + P3P2G1 + P3P2P1C0G4 = G4 + P4G3 + P4G3G2 + P4P3P2G1 + P4P3P2P1C03.Suppose a puter with a clock frequency of 100 MHz as four types of instructions, and the frequency of usage and the CPI for

4、each of them are given in table. Instruction operationFrequency of usageCycles per instructionArithmetic-logic40%2Load/store30%4pare8%2.5branch22%3(1) Find the MIPS of the puter and the T (CPU time) required to run a program of 107 instructions.(2) bining paring and branch instructions together so t

5、hat pare instructions can be replaced and removed. Suppose each pare instruction was originally used with one branch instruction, and now each branch instruction is changed to a pare&branch instruction. Also suppose that the new proposal would decrease the clock frequency by 5%, because the new pare

6、&branch instruction needs more time to execute. Find the new CPIave, MIPS, and T. CPIave = (0.4*2+0.*4+0.22*3)/0.92 = 2.9MIPS = f(MHz)/CPIave = (100*0.95)/2.9 = 32.76T = IC CPIave/f(Hz) = 0.92*10000000*2.9/0.95*100*1000000= 0.28s4 CPU has 16 address bus lines (A15-A0), 8 data bus lines (D7-D0), R/W

7、(high level represents Read, while low level represents Write), MREQ control line for accessing memory (low level represents accessible).Memory space allocation: The minimal 8K are used for system program, which is posed of Read Only Memory chip; the following 24K are used for user program; the last

8、 2K are used for system working. Now we have: EPROM 8K * 8 (contains CS control line only);SRAM 16K*1, 2K*8, 4K*8, 8K*8;Decoder 74LS138;and other logic gates Questions:(1) Select appropriate chips to form the required memory space. Which chips are needed? How many chips are needed? Descript the corr

9、esponding data bus length, address bus length and control bus line.(2) Descript the address distribution of memory.(3) Descript select chip logic functions (片选逻辑函数) of each chip.(4) Descript the connection way among CPU, memory chips and 74LS138.解：1根据给定条件，选用EPROM：8K8位芯片1片，其地址线13根，数据线8根，片选控制信号CS，无读写控

10、制信号。SRAM： 8K8位芯片3片，地址线13根，数据线8根，片选控制线号CS，读写控制线号R/W；2K8位芯片1片，地址线11根，数据线8根，片选控制线号CS，读写控制线号R/W。2A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 08K 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1CS1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 08K 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1CS2 0 1 0 0 0 0

11、0 0 0 0 0 0 0 0 0 08K 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1CS3 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 08K 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1CS4 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 02K 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1(3) CS0 = (A15*A14*A13) = Y0 CS1 = (A15*A14*A13) = Y1 CS2 = (A15*A14*A13) = Y2 CS3 = (A15*A14*A13) = Y3 CS4 =

12、 (A15*A14*A13)*(A12*A11) =( (Y1)*A12*A11)(4) 数据总线：由于选择的存储芯片数据总线与CPU数据总线都是8位，因此不需要进展扩展，一一对应D7D0相联即可。地址总线：系统程序区使用EPROM 8K容量，所以CPU的A12A0到EPROM的片地址总线A12A0，CPU的A15A13地址线经过74LS138译码，输出Y0连接到EPROM的片选； 用户程序区使用3片SRAM 各8K容量，所以CPU的A12A0到SRAM的片地址总线A12A0，CPU的A15A13地址线经过74LS138译码，输出Y1、Y2、Y3分别连接到3片SRAM的片选。系统工作区使用SR

13、AM 2K容量，所以CPU的A10A0到SRAM的片地址总线A10A0，CPU的A15A13地址线经过74LS138译码，输出的Y7取反，与A12、A11相与，再取反连接到2K的SRAM片选。5. CPU performs a program; it accesses cache 3800 and accesses main memory 200. Known that Tc = 50ns, Tm = 250ns. Solving that the efficiency (e) and Ta of the cache/memory system.命中率 H = Ne / NC + Nm = 3

14、800 / (3800 + 200) = 0.95主存慢于cache的倍率 ：r = tm / tc= 250ns / 50ns = 5访问效率 ：e = 1 / r + (1 r)H= 1 / 5 + (1 5)0.95 = 83.3%平均访问时间 ：ta = tc / e = 50ns / 0.833 = 60ns6.We use 16M*8bit memory chip to form a 64M*16bit main memory module. Required that the capacity of storage be expand, the access time be re

15、duced.Questions: (1) How many 16M*8bit memory chips should be used?(2) Give the address length of each memory chip and address length of main memory module.(3) Descript select chip logic functions (片选逻辑函数) of each chip. Descript the connection way among encoder, CPU and memory chips.(4)For an addres

16、s (2345678)16, give its body number and address inside the body.(1)8个(2)存储器芯片的地址长度为24位。主存储器的地址长度为26位(3)每两片16M*8的芯片组成一组，每组构成一个16位的存储芯片，A2A25连接新的芯片组的地址位。A0A1分别连接译码器，译码器连接CS0CS1CS2CS3。(4) 1234567右移两位是48D159，所以其体地址为：48D159 最低两位是11B，所以其体号为3 。7.Known that efficiency of a cache/memory system is 0.85, Ta =

17、60ns, and cache is 4 times faster than memory. Solving that Tm and hit ratio of cache.因为：ta= tc / e所以 ：tc= tae= 600.85 = 510ns (cache存取周期)tm= tcr =510 4 = 204ns (主存存取周期)因为：e = 1 / r+(1 r)H 所以： H= 2.4 / 2.55 = 0.948.Main memory of a puter has cache and primary memory. Known that Tc = 45ns, Tm = 200ns

18、. In a period of time, CPU accesses main memory 4500 and including accesses primary memory 340. Question:(1) Hit ratio of cache;(2) Ta;(3) The efficiency (e).(1)cache的命中率H=Nc/(Nc+Nm)=0.92(2)CPU访存的平均时间Ta=HTc+(1-H)Tm=0.9245+(1-0.92)200=57.4ns(3)Cache-主存系统的效率e=Tc/Ta=0.78=78%9.CPU has 16 address bus lin

19、es (A15-A0), 8 data bus lines (D7-D0), R/W (high level represents Read, while low level represents Write), MREQ control line for accessing memory (low level represents accessible).Memory space allocation: The minimal 4K are used for system program, which is posed of Read Only Memory chip; the follow

20、ing 4K are used for user program; the last 16K are used for system working. Questions:(1) As shown in figures, select appropriate chips to form the required memory space. Which chips are needed? How many chips are needed? Descript the corresponding data bus length, address bus length and control bus

21、 line.(2) Descript the address distribution of memory.(3) Descript select chip logic functions (片选逻辑函数) of each chip.(4) Descript the connection way among 74LS138, CPU and memory chips.解：1根据给定条件，选用RAM(16K)：8K8位芯片2片，其地址线13根，数据线8根，片选控制信号CS，读写控制线号R/W。RAM(4K)：4K4位芯片2片，地址线12根，数据线8根，片选控制线号CS，读写控制线号R/W；ROM

22、(4K):2K8位芯片1片，地址线11根，数据线8根，片选控制线号CS，无读写控制信号。2A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 08K 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1CS1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 08K 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1CS2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 08K 1 1 0 1 1 1 1 1 1 1 1 1 1

23、1 1 1CS3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 08K 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1CS4 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 02K 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 12K 1 1 1 1 0000000000002K 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1(3) CS0 = Y0 CS1 = Y1 CS2 = Y7+A12 CS3 = Y7+A12+A11 CS4 = Y7+A12+A11(4) 数据总线：由于选择的存储芯片数据总线与CPU数据总线都是

24、8位，因此不需要进展扩展，一一对应D7D0相联即可。地址总线：系统程序区使用EPROM 8K容量，所以CPU的A12A0到EPROM的片地址总线A12A0，CPU的A15A13地址线经过74LS138译码，输出Y0连接到EPROM的片选； 用户程序区使用3片SRAM 各8K容量，所以CPU的A12A0到SRAM的片地址总线A12A0，CPU的A15A13地址线经过74LS138译码，输出Y1、Y2、Y3分别连接到3片SRAM的片选。系统工作区使用SRAM 2K容量，所以CPU的A10A0到SRAM的片地址总线A10A0，CPU的A15A13地址线经过74LS138译码，输出的Y7取反，与A12

25、、A11相与，再取反连接到2K的SRAM片选。10.CPU performs a program; it accesses cache 5000 and accesses main memory 200. Known that Tc = 40ns, Tm = 160ns. Solve:(1) Hit ratio of cache;(2) The efficiency (e);(3) Ta. 命中率 H = Nc/Nc+Nm = 5000/5000+200=5000/5200=0.96 主存慢于cache的倍率 R = Tm/Tc=160ns/40ns=4访问效率：r + (1-r) h14 +

26、 (1-4) 0.9689.3平均访问时间400.89345ns11. For cache, its hit ratio is 98%, CPU accesses main memory slower than cache 4 times. Let Tm=200ns, solving the efficiency (e) and average access time(Ta) of cache/memory system. R=Tm/Tc=4；Tc=Tm/4=50nsE=1/R+1-RH=1/4+1-40.98=0.94Ta=Tc/E=Tc4-30.98= 501.06=53ns。12. Gi

27、ven a decimal number 20.59375, represent it as a normalized single-precision floating-point number in IEEE 754 standard format.(20.59375)10=(10100.10011)2Move decimal ：1.010010011*24 e=4S=0 , E=4+127=131 , M=010010011Answer ：0100 0001 1010 0100 1100 0000 0000 0000=41A4C0001613.Given: x= 0.1011，y = - 0.0101Ask: 1/2x 2s pl，1/4x 2s pl， - x 2s pl，1/2y 2s pl，1/4y 2s pl， - y 2s pl1/2 x 2s pl=0.010111/4 x 2s pl=0.001011 - x 2s pl=1.01011/2 y 2s pl=1.110111/4 y 2s pl=1.111011 - y 2s pl=0.0101. . word.zl-