MIPI协议详细介绍.pptx

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1、What is MIPI?v MIPI stands for Mobile Industry Processor Interface MIPI Alliance is a collaboration of mobile industry leaders.Objective to promote open standards for interfaces to mobile application processors.Intends to speed deployment of new services to mobile users by establishing Spec.v Board

2、Members in MIPI Alliance Intel,Motorola,Nokia,NXP,Samsung,ST,TI第1页/共31页What is MIPI?v MIPI Alliance Specification for display DCS(Display Command Set)DCS is a standardized command set intended for command mode display modules.DBI,DPI(Display Bus Interface,Display Pixel Interface)DBI：Parallel interfa

3、ces to display modules having display controllers and frame buffers.DPI：Parallel interfaces to display modules without on-panel display controller or frame buffer.DSI,CSI(Display Serial Interface,Camera Serial Interface)DSI specifies a high-speed serial interface between a host processor and display

4、 module.CSI specifies a high-speed serial interface between a host processor and camera module.D-PHY D-PHY provides the physical layer definition for DSI and CSI.第2页/共31页DSI LayersDCS specDSI specD-PHY spec第3页/共31页OutlineD-PHYIntroductionLane Module,State and Line levelsOperating ModesEscape ModeSys

5、tem Power StatesElectrical CharacteristicsSummary第4页/共31页Introduction for D-PHYD-PHY describes a source synchronous,high speed,low power,low cost PHYA PHY configuration containsA Clock LaneOne or more Data LanesThree main lane typesUnidirectional Clock LaneUnidirectional Data LaneBi-directional Data

6、 LaneTransmission ModeLow-Power signaling mode for control purpose：10MHz(max)High-Speed signaling mode for fast-data traffic：80Mbps 1Gbps per LaneD-PHY low-level protocol specifies a minimum data unit of one byteA transmitter shall send data LSB first,MSB last.D-PHY suited for mobile applicationsDSI

7、：Display Serial InterfaceA clock lane,One to four data lanes.CSI：Camera Serial Interface第5页/共31页Two Data Lane PHY Configuration第6页/共31页Lane ModulePHY consists of D-PHY(Lane Module)D-PHY may containLow-Power Transmitter(LP-TX)Low-Power Receiver(LP-RX)High-Speed Transmitter(HS-TX)High-Speed Receiver(H

8、S-RX)Low-Power Contention Detector(LP-CD)Three main lane typesUnidirectional Clock LaneMaster：HS-TX,LP-TXSlave：HS-RX,LP-RXUnidirectional Data LaneMaster：HS-TX,LP-TXSlave：HS-RX,LP-RXBi-directional Data LaneMaster,Slave：HS-TX,HS-RX,LP-TX,LP-RX,LP-CD第7页/共31页Universal Lane Module Architecture第8页/共31页Lan

9、e States and Line LevelsThe two LP-TXs drive the two Lines of a Lane independently and single-ended.Four possible Low-Power Lane states(LP-00,LP-01,LP-10,LP-11)A HS-TX drives the Lane differentially.Two possible High Speed Lane states(HS-0,HS-1)During HS transmission the LP Receivers observe LP-00 o

10、n the LinesLine Levels(typical)LP：01.2VHS：100300mV(Swing：200mV)Lane StatesLP-00,LP-01,LP-10,LP-11HS-0,HS-1第9页/共31页Operating ModesThere are three operating modes in Data LaneEscape mode,High-Speed(Burst)mode and Control modePossible events starting from the Stop State of control modeEscape mode reque

11、st(LP-11LP-10LP-00LP-01LP-00)High-Speed mode request(LP-11LP-01LP-00)Turnaround request(LP-11LP-10LP-00LP-10LP-00)第10页/共31页Escape ModeEscape mode is a special operation for Data Lanes using LP states.With this mode some additional functionality becomes available：LPDT,ULPS,TriggerA Data Lane shall en

12、ter Escape mode via LP-11LP-10LP-00LP-01LP-00Once Escape mode is entered,the transmitter shall send an 8-bit entry command toindicate the requested action.Escape mode uses Spaced-One-Hot Encoding.means each Mark State is interleaved with a Space State(LP-00).Send Mark-0/1 followed by a Space to tran

13、smit a zero-bit/one-bitA Data Lane shall exit Escape mode via LP-10LP-11Ultra-Low Power StateDuring this state,the Lines are in the Space state(LP-00)Exited by means of a Mark-1 state with a length TWAKEUP(1ms)followed by a Stop state.第11页/共31页Escape Mode第12页/共31页Clock Lane Ultra-Low Power State A C

14、lock Lane shall enter ULPS viaLP-11LP-10LP-00 exited by means of a Mark-1 with a length TWAKEUP followed by a Stop StateLP-10 TWAKEUP LP-11The minimum value of TWAKEUP is 1ms第13页/共31页High-Speed Data Transmission The action of sending high-speed serial data is called HS transmission or burst.Start-of

15、-TransmissionLP-11LP-01LP-00SoT(0001_1101)HS Data Transmission BurstAll Lanes will start synchronouslyBut may end at different timesThe clock Lane shall be in High-Speed mode,providing a DDR Clock to the Slave sideEnd-of-TransmissionH Toggles differential state immediately after last payload data bi

16、t and keeps that state for a time THS-TRAIL第14页/共31页High-Speed Clock Transmission Switching the Clock Lane between Clock Transmission and LP ModeA Clock Lane is a unidirectional Lane from Master to SlaveIn HS mode,the clock Lane provides a low-swing,differential DDR clock signal.the Clock Burst alwa

17、ys starts and ends with an HS-0 state.the Clock Burst always contains an even number of transitions第15页/共31页Summary for D-PHY Lane Module,Lane State and Line LevelsLane Module：LP-TX,LP-RX,HS-TX,HS-RX,LP-CDLane States：LP-00,LP-01,LP-10,LP-11,HS-0,HS-1Line Levels(typical)：LP：01.2V,HS：100300mV(Swing：20

18、0mV)Operating ModesEscape Mode entry procedure：LP-11LP-10LP-00LP-01LP-00Entry Code LPD(10MHz)Escape Mode exit procedure：LP-10LP-11High Speed Mode entry procedure：LP-11LP-01LP-00SoT(00011101)HSD(80Mbps 1Gbps)High Speed Mode exit procedure：EoTLP-11Control Mode-BTA transmission procedure：LP-11LP-10LP-0

19、0LP-10LP-00Control Mode-BTA receive procedure：LP-00LP-10LP-11System Power StatesLow-Power mode,High-Speed mode,Ultra-Low Power modeFault DetectionContention Detection(LP-CD),Watchdog Timer,Sequence Error Detection(Error Report)Global Operation Timing ParameterClock Lane Timing,Data Lane TimingOther

20、Timing Initialization,BTA,Wake-Up from ULPSElectrical CharacteristicsHS-RX,LP-RX,LP-TX,LP-CD,Pin characteristic,Clock signal,Data-Clock timingDC and AC characteristic第16页/共31页OutlinevDSIIntroductionLane Distributor/Merger ConceptualPacket StructureData Transmission WayProcessor-Sourced PacketsPeriph

21、eral-Sourced PacketsReverse-Direction LP TransmissionVideo ModeSummary第17页/共31页Introduction for DSI DSI is a Lane-scalable interface for increased performance.One Clock Lane/One to Four Data LanesDSI-compliant peripherals support either of two basic modes of operationCommand Mode(Similar to MPU IF)D

22、ata Lane 0：bidirectionalFor returning data,ACK or error report to hostAdditional Data Lanes：unidirectional.Video Mode(Similar to RGB IF)Data Lane 0：bidirectional or unidirectional;Additional Data Lanes：unidirectional.Video data should only be transmitted using HS mode.Transmission ModeHigh-Speed sig

23、naling modeLow-Power signaling modeForward/Reverse direction LP transmissions shall use Data Lane 0 onlyFor returning data,DSI-compliant systems shall only use Data Lane 0 in LP ModePacket TypesShort Packet：4 bytes(fixed length)Long Packet：665541 bytes(variable length)第18页/共31页Two Data Lanes HS Tran

24、smission Example第19页/共31页Data Transmission WayvSeparate TransmissionsvSeparate Transmissions KEY:LPS Low Power State SP Short PacketSoT Start of Transmission LgP Long PacketEoT End of Transmission第20页/共31页Short Packet Structure Packet Header(4 bytes)Data Identifier(DI)*1byte：Contains the Virtual Cha

25、nnel7:6 and Data Type5:0.Packet Data*2byte：Length is fixed at two bytesError Correction Code(ECC)*1byte：allows single-bit errors to be corrected and 2-bit errors to be detected.Packet SizeFixed length 4 bytesThe first byte of any packet is the DI(Data Identifier)byte.DI7:6：These two bits identify th

26、e data as directed to one of four virtual channels.DI5:0：These six bits specify the Data Type.第21页/共31页Long Packet StructurePacket Header(4 bytes)Data Identifier(DI)*1byte：Contains the Virtual Channel7:6 and Data Type5:0.Word Count(WC)*2byte：defines the number of bytes in the Data Payload.Error Corr

27、ection Code(ECC)*1byte：allows single-bit errors to be corrected and 2-bit errors to be detected.Data Payload(065535 bytes)Length=WC bytesPacket Footer(2 bytes)：ChecksumIf the payload has length 0,then the Checksum calculation results in FFFFhIf the Checksum isnt calculated,the Checksum value is 0000

28、hPacket Size4+(065535)+2=6 65541 bytes第22页/共31页Data Types for Processor-sourced Packets第23页/共31页Error Correction Code P7=0 P6=0 P5=D10D11D12D13D14D15D16D17D18D19D21D22D23 P4=D4D5D6D7D8D9D16D17D18D19D20D22D23 P3=D1D2D3D7D8D9D13D14D15D19D20D21D23 P2=D0D2D3D5D6D9D11D12D15D18D20D21D22 P1=D0D1D3D4D6D8D10

29、D12D14D17D20D21D22D23 P0=D0D1D2D4D5D7D10D11D13D16D20D21D22D23第24页/共31页Checksumunsigned char xx=0 x01,0 x5a,0 x5a,0 x03,0 x08,0 x2A,0 x00,0 x01 ,0 x00,0 xF8,0 x00,0 xF6,0 x57,0 x00,0X00,0 xE5;typedef unsigned short U16;typedef unsigned char U8;U16 CRC_test;U16 crc16_update(U16 crc,U8 a);int main()U16

30、 crc,i;crc=0 xFFFF;for(i=0;i1;i+)crc=crc16_update(crc,xxi);CRC_test=crc;vU16 crc16_update(U16 crc,U8 a)vv int i;v crc=a;v for(i=0;i 1)0 x8408;v else crc=(crc 1);v v return crc;v第25页/共31页Peripheral-to-Processor LP TransmissionsDetailed format descriptionPacket structure for peripheral-to-processor tr

31、ansactions is the same as forthe processor-to-peripheral direction For a single-byte read response,valid data shall be returned in the first byte The second byte shall be sent as 00hIf the peripheral does not support Checksum it shall return 0000h第26页/共31页Peripheral-to-Processor LP TransmissionsPeri

32、pheral-to-processor transactions are of four basic typesTearing Effect(TE)：trigger message(BAh)Acknowledge：trigger message(84h)Acknowledge and Error Report：short packet(Data Type is 02h)Response to Read Request：short packet or long packetGeneric Read Response、DCS Read Response（1byte,2byte,multi byte

33、）FeatureBTA shall take place after every peripheral-to-processor transactionMulti-Lane systems shall use Lane 0 for all peripheral-to-processor transmissionsReverse-direction signaling shall only use LP mode of transmission第27页/共31页Video ModeDSI supports three formats for Video Mode data transmissio

34、nNon-Burst Mode with Sync PulsesNon-Burst Mode with Sync EventsBurst Mode第28页/共31页Summary for DSIDSI is a Lane-scalable interface.One Clock LaneOne to Four Data LanesTransmission ModeHigh-Speed signaling mode(differential signal)(100mV300mV)Low-Power signaling mode(single-ended signal)(0V1.2V)For re

35、turning data,only use Data Lane 0 in LP ModePacket TypesShort Packet：4 bytes(fixed length)Data ID(1byte)+Data0(1byte)+Data1(1byte)+ECC(1byte)Long Packet：665541 bytes(variable length)Packet Header(4 bytes)+Data Payload(065535 bytes)+Packet Footer(2 bytes)Operation ModeCommand Mode(Similar to MPU IF)Video Mode(Similar to RGB IF)Non-Burst Mode with Sync PulsesNon-Burst Mode with Sync EventsBurst Mode第29页/共31页 Thank you!第30页/共31页谢谢您的观看！第31页/共31页