静态时序分析基本原理和时序分析模型.ppt

《静态时序分析基本原理和时序分析模型.ppt》由会员分享，可在线阅读，更多相关《静态时序分析基本原理和时序分析模型.ppt（26页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、2009AlteraCorporation1QuartusQuartus II Software Design II Software Design Series:Timing AnalysisSeries:Timing Analysis-Timing analysis basicsTiming analysis basics2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation2ObjectivesnDispl

2、ayacompleteunderstandingoftiminganalysis2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation3How does timing verification work?nEverydevicepathindesignmustbeanalyzedwithrespecttotimingspecifications/requirements-Catchtiming-relateder

3、rorsfasterandeasierthangate-levelsimulation&boardtestingnDesignermustentertimingrequirements&exceptions-Usedtoguidefitterduringplacement&routing-UsedtocompareagainstactualresultsINCLKOUTDQCLRPREDQCLRPREcombinationaldelaysCLR2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,

4、andMegaCorearetrademarksofAlteraCorporation4Timing Analysis BasicsnLaunchvs.latchedgesnSetup&holdtimesnData&clockarrivaltimenDatarequiredtimenSetup&holdslackanalysisnI/OanalysisnRecovery&removalnTimingmodels2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetra

5、demarksofAlteraCorporation5Path&Analysis TypesThreetypesofPaths:1.ClockPaths2.DataPath3.AsynchronousPaths*ClockPathsAsyncPathDataPathAsyncPathDQCLRPREDQCLRPRETwotypesofAnalysis:1.Synchronousclock&datapaths2.Asynchronous*clock&asyncpaths*Asynchronous refers to signals feeding the asynchronous control

6、 ports of the registers2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation6Launch&Latch EdgesCLKLaunch Launch EdgeEdgeLatch Latch EdgeEdgeDataValidDATALaunchEdge:theedgewhich“launches”thedatafromsourceregisterLatchEdge:theedgewhich“

7、latches”thedataatdestinationregister(withrespecttothelaunchedge,selectedbytiminganalyzer;typically1cycle)2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation7Setup&HoldSetup:TheminimumtimedatasignalmustbestableBEFOREclockedgeHold:The

8、minimumtimedatasignalmustbestableAFTERclockedgeDQCLRPRECLKThValidDATATsuCLKDATATogether,the setup time and hold time form a Data Required Window,the time around a clock edge in which data must be stable.2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetradema

9、rksofAlteraCorporation8Data Arrival TimeDataArrivalTime=launchedge+Tclk1+Tco+TdataCLKREG1.CLKTclk1DataValidREG2.DTdataLaunchEdgeDataValidREG1.QTconThetimefordatatoarriveatdestinationregistersDinputREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdata2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,Ha

10、rdCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation9Clock Arrival TimeClockArrivalTime=latchedge+Tclk2CLKREG2.CLKTclk2LatchEdgenThetimeforclocktoarriveatdestinationregistersclockinputREG1PREDQCLRREG2PREDQCLRComb.LogicTclk22009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nio

11、s,Quartus,andMegaCorearetrademarksofAlteraCorporation10Data Required Time-SetupDataRequiredTime=ClockArrivalTime-Tsu-SetupUncertaintyCLKREG2.CLKTclk2LatchEdgenTheminimumtimerequiredforthedatatogetlatchedintothedestinationregisterTsuDataValidREG2.DDatamustbevalidhereREG1PREDQCLRREG2PREDQCLRComb.Logic

12、Tclk2Tsu2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation11Data Required Time-HoldDataRequiredTime=ClockArrivalTime+Th+HoldUncertaintyCLKREG2.CLKTclk2LatchEdgenTheminimumtimerequiredforthedatatogetlatchedintothedestinationregister

13、ThDatamustremainvalidtohereDataValidREG2.DREG1PREDQCLRREG2PREDQCLRComb.LogicTclk2Th2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation12Tclk2Setup SlackREG2.CLKnThemarginbywhichthesetuptimingrequirementismet.Itensureslauncheddataarr

14、ivesintimetomeetthelatchingrequirement.TsuCLKREG1.CLKTclk1DataValidREG2.DTdataDataValidREG1.QTco Setup SlackLaunchEdgeLatchEdgeREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdataTclk2Tsu2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporatio

15、n13Setup Slack(contd)Positiveslack-TimingrequirementmetNegativeslack-TimingrequirementnotmetSetup Slack=Data Required Time Data Arrival Time2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation14Hold SlackREG2.CLKTclk2nThemarginbywhic

16、htheholdtimingrequirementismet.Itensureslatchdataisnotcorruptedbydatafromanotherlaunchedge.ThCLKREG1.CLKTclk1DataValidREG2.DTdataDataValidREG1.QTcoHoldSlackLatchEdgeNextLaunchEdgeREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdataTclk2Th2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios

17、,Quartus,andMegaCorearetrademarksofAlteraCorporation15Hold Slack(contd)Positiveslack-TimingrequirementmetNegativeslack-TimingrequirementnotmetHold Slack=Data Arrival Time Data Required Time2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCor

18、poration16FPGA/CPLD or ASSPASSP or FPGA/CPLDI/O Analysis nAnalyzingI/Operformanceinasynchronousdesignusesthesameslackequations-Mustincludeexternaldevice&PCBtimingparametersreg1PREDQCLRreg2PREDQCLRCL*TdataTclk1Tclk2TCOTsu/ThOSCDataArrivalPathDataArrivalPathDataRequiredPath*Represents delay due to cap

19、acitive loading2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation17Recovery&RemovalRecovery:TheminimumtimeanasynchronoussignalmustbestableBEFOREclockedgeRemoval:TheminimumtimeanasynchronoussignalmustbestableAFTERclockedgeDQCLRSETCL

20、KTremValidASYNCTrecCLKASYNC2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation18Asynchronous=Synchronous?nAsynchronouscontrolsignalsourceisassumedsynchronous-Slackequationsstillapplyldataarrivalpath=asynchronouscontrolpathlTsuTrec;T

21、hTrem-Externaldevice&boardtimingparametersmaybeneeded(Ex.1)ASSPreg1PREDQCLRFPGA/CPLDreg2PREDQCLROSCFPGA/CPLDreg1PREDQCLRreg2PREDQCLRExample1Example2Data arrival pathData arrival pathData required pathData required path2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMeg

22、aCorearetrademarksofAlteraCorporation19Why Are These Calculations Important?nCalculationsareimportantwhentimingviolationsoccur-NeedtobeabletounderstandcauseofviolationnExamplecauses-Datapathtoolong-Requirementtooshort(incorrectanalysis)-Largeclockskewsignifyingagatedclock,etc.nTimeQuesttiminganalyze

23、rusesthem-Equationstocalculateslack-Terminology(launchandlatchedges,DataArrivalPath,DataRequiredPath,etc.)intimingreports2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation20Timing Models in DetailnQuartusIIsoftwaremodelsdevicetimin

24、gattwoPVTconditionsbydefault-Slow CornerModellIndicatesslowestpossibleperformanceforanysinglepathlTimingforslowestdeviceatmaximumoperatingtemperatureandVCCMIN-Fast CornerModellIndicatesfastestpossibleperformanceforanysinglepathlTimingforfastestdeviceatminimumoperatingtemperatureandVCCMAXnWhytwocorne

25、rtimingmodels?-Ensuresetuptimingismetinslowmodel-EnsureholdtimingismetinfastmodellEssentialforsourcesynchronousinterfacesnThirdmodel(slow,min.temp.)availableonlyfor65nmandsmallertechnologydevices(temperatureinversionphenomenon)2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quart

26、us,andMegaCorearetrademarksofAlteraCorporation21Generating Fast/Slow NetlistnSpecifyoneofthedefaulttimingmodelstobeusedwhencreatingyournetlistnDefaultistheslowtimingnetlistnTospecifyfasttimingnetlist-Use-fast_modeloptionwithcreate_timing_netlistcommand-ChooseFast cornerinGUIwhenexecutingCreate Timin

27、g NetlistfromNetlistmenu-CANNOTselectfastcornerfromTasksPane2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation22Specifying Operating Conditions nPerformtiminganalysisfordifferentdelaymodelswithoutrecreatingtheexistingtimingnetlistn

28、TakesprecedenceoveralreadygeneratednetlistnRequiredforselectingslow,min.temp.modelandothermodels(industrial,military,etc.)dependingondevicenUseget_available_operating_conditionstoseeavailableconditionsfortargetdevice2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaC

29、orearetrademarksofAlteraCorporationReference DocumentsReference DocumentsnQuartusIIHandbook,Volume3,Chapter7TheQuartusIITimeQuestTimingAnalyzernQuickStartTutorialnCookbook2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporationReference

30、DocumentsReference DocumentsnSDCandTimeQuestAPIReferenceManualnAN481:ApplyingMulticycleExceptionsintheTimeQuestTimingAnalyzernAN433:ConstrainingandAnalyzingSource-SynchronousInterfaces2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporat

31、ion25Instructor-Led TrainingWithAlterasinstructor-ledtrainingcourses,youcan:ListentoalecturefromanAlteratechnicaltrainingengineer(instructor)Completehands-onexerciseswithguidancefromanAlterainstructorAskquestions&receivereal-timeanswersfromanAlterainstructorEachinstructor-ledclassisoneortwodaysinlen

32、gth(8workinghoursperday).Online TrainingWithAlterasonlinetrainingcourses,youcan:TakeacourseatanytimethatisconvenientforyouTakeacoursefromthecomfortofyourhomeoroffice(noneedtotravelaswithinstructor-ledcourses)Eachonlinecoursewilltakeapproximateonetothreehourstocomplete.Viewtrainingclassschedule®is

33、terforaclassLearn More Through Technical Training2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation26Altera Technical SupportnReferenceQuartusIIsoftwareon-linehelpnQuartusIIHandbooknConsultAlteraapplications(factoryapplicationsengineers)-MySupport:-Hotline:(800)800-EPLD(7:00a.m.-5:00p.m.PST)nFieldapplicationsengineers:contactyourlocalAlterasalesofficenReceiveliteraturebymail:(888)3-ALTERAnFTP:nWorld-wideweb:-Usesolutionstosearchforanswerstotechnicalproblems-Viewdesignexamples