FPGAandISE基础教程学习.pptx

《FPGAandISE基础教程学习.pptx》由会员分享，可在线阅读，更多相关《FPGAandISE基础教程学习.pptx（34页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、contentWhatistheFPGAFPGAdesignflowProjectenvironment：ISE14.7VerilogexamplesFunctionalsimulationProgramanddebug第1页/共34页WHATIStheFPGAPart of the Graphite circuitWhat can FPGA do?FPGA:Field Programmable Gate arrayPLD:Programmable Logic DeviceCPLD:Complex Programmable Logic Device第2页/共34页WHATIStheFPGA I

2、/O:I/O:pinsconnectedtoperipheralcircuitPLL:frequencymultiplication,frequencydemultiplicationandphaseshiftMUTIPLIERM4KBLOCK:Memoryblock,forRAMROMandFIFOdesign LOGICARRAYLOGICARRAYForcombinatorylogicandtriggerdesign Programanddebugblock:Programanddebugblock:Structure of FPGA第3页/共34页WHATIStheFPGASummar

3、yofspartan-3AFPGAattributesNOTECLB:configurable logic blockDCM:digital clock managerDevice utilization of Graphite FPGA(XC3S400A)第4页/共34页FPGADESIGNFLOWimplementationFunctional descriptionlReference to hw spec.&FPGA spec.Design inputlSchematic or HDL(RTL)lPin assignmentPlanner or TCL scriptSynthesisl

4、Output gate-level netlist based on some kind of FPGAlLogical description to specific devicesPlace&routeDownload and verify第5页/共34页FPGADESIGNFLOWverificationThree key verification points for FPGA implementationlBehavioral simulationlPost-place&route static timing analysislDownload and verify in circu

5、itPost-synthesis gate-level simulation and post-place&route timing simulations can be done for production sign offlPost-place&route timing simulations are also often done to verify board-and system-level timing6第6页/共34页IDE(integrateddevelopmentenvironment)THEMAININTERFACEOFISE14.7第7页/共34页DesignSpec.

6、andprocessBVT FPGA design processReference Documents:HW spec.SchematicFPGA spec.FPGA design processGraphite documents第8页/共34页1,Create a new project2,Project name,location and source type3,Chose device and toolsIDE:CREATE A NEW PROJECT4,Finish第9页/共34页IDEAnewproject工程名工程名器件名字器件名字生成了空的工程框架生成了空的工程框架第10页

7、/共34页ideCreate/addnewsource第11页/共34页IDEAcompletedproject第12页/共34页projectfiles(*.v)模块开始和结束（figure 1）变量声明（figure 2）数据流语句低层模块实例（figure3）行为描述块任务和函数Figure 1Figure 3Figure 2第13页/共34页VerilogstandardpurposePurpose:LessspaceHighersanitaryEasytoanalyzeanddebugEasytoreadandunderstandPortability第14页/共34页Verilog

8、standardStandardizeddesign结构层次化命名规范化常量参数化其他Clock：避免混合时钟，避免门控时钟，单模块单时钟Reset：避免模块内部产生Always：敏感变量完备化第15页/共34页projectfiles（*.ucf）第16页/共34页SchematicviewStep1:view schematicStep2:choose start up第17页/共34页SchematicviewChoose elements to create schematic第18页/共34页SchematicviewGraphite signal:第19页/共34页Function

9、alsimulation第20页/共34页Functionalsimulation第21页/共34页Functionalsimulation第22页/共34页Simulationtool：isimGraphite：PID_LED_CONTROL simulation第23页/共34页ReferencedocumentsFigure:LED control,from Graphite schematicFigure:led behavior description,from Graphite FPGA spec.第24页/共34页Simulationtool：isimGraphite：reset

10、 timing simulation第25页/共34页ProgramanddebugcompileFailedsuccessful第26页/共34页Programanddegubstartimpact第27页/共34页impactselect/addstoragedevice第28页/共34页impactgeneratingpromfile*.mcs*.mcs filefile*.xsvf*.xsvf file第29页/共34页DownloadandprogramJTAG chain scanning第30页/共34页DownloadandprogramChoose the programmable image第31页/共34页DownloadandprogramProgram Verify it Verify it on your on your board!board!第32页/共34页第33页/共34页感谢您的观看！第34页/共34页