嵌入式系统接口设计与应用2课件.pptx

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1、STM32F103MCU本课程的主要内容第1页/共287页主要内容Cortex-M3的总结STM32F系列的特点STM32F103系列的特点STM32F103的概述STM32F103的外特性STM32F103的内特性STM32F103的SFRSTM32F103的应用第2页/共287页主要参考资料STM32F103xxx_Datasheet.pdfSTM32F103xxx_Reference_Manual.pdfSTM32F103xxx_Library_Manual.pdfRVMDK 3.2第3页/共287页Cortex-M3的总结Cortex-M3的总结CM3NVIC第4页/共287页Cort

2、ex-M3的总结Cortex-M3的特性Cortex-M3 block diagram第5页/共287页Cortex-M3的总结Cortex-M3的特性Processor coreARMv7-M architecture.The main features:Thumb-2 instruction set subset.Harvard Architecture with data load/store.Three-stage pipeline.Single cycle 32-bit multiply.Hardware divide.Thumb and Debug states.Handler m

3、odes and Thread modes.without the overhead of state saving and restoration between interrupts.Interruptible-continued LDM/STM,PUSH/POP.ARMv6 compatible BE8 and LE access support.ARMv6 compatible unaligned access support.第6页/共287页Cortex-M3的总结Cortex-M3的特性Processor coreARMv7-M architecture.The main fea

4、tures:Low latency ISR entry and exit.Processor state saving and restoration,with no instruction fetch overhead.Exception vector is fetched from memory in parallel with the state saving,enabling faster ISR entry.Support for late arriving(迟来)interrupts.Tightly coupled interface to interrupt controller

5、 enabling efficient processing of late-arriving(迟来)interrupts.Tail-chaining(尾连)of interrupts,enabling back-to-back(背靠背)interrupt processing第7页/共287页Cortex-M3的总结Cortex-M3的特性Processor coreRegisters The processor contains:13 general purpose 32-bit registers,R0 to R12Link Register(LR)-R14Program Counter

6、(PC)-R15Program Status Register,xPSRtwo banked SP registers.-R13第8页/共287页Cortex-M3的总结Cortex-M3的特性Processor coreMemory interfaceThe processor has a Harvard interface to enable simultaneous instruction fetches with data load/stores.Memory accesses are controlled by:A separate Load Store Unit(LSU)that

7、decouples load and store operations from the Arithmetic and Logic Unit(ALU).A 3-word entry Prefetch Unit(PFU).One word is fetched at a time.This can be two Thumb instructions:one word-aligned Thumb 32-bit instruction;the upper/lower halfword of a halfword-aligned Thumb 32-bit instruction with one Th

8、umb instruction,or the lower/upper halfword of another halfword-aligned Thumb 32-bit instruction.第9页/共287页Cortex-M3的总结Cortex-M3的特性Processor coreNVICThe NVIC is tightly coupled to the processor core.This facilitates low latency exception processing.The main features include:a configurable number of e

9、xternal interrupts,from 1 to 240a configurable number of bits of priority,from three to eight bitslevel and pulse interrupt supportdynamic reprioritization of interruptspriority groupingsupport for tail-chaining of interruptsprocessor state automatically saved on interrupt entry,and restored on inte

10、rrupt exit,with no instruction overhead.第10页/共287页Cortex-M3的总结Cortex-M3的特性Processor coreBus matrixThe bus matrix connects the processor and debug interface to the external buses.The bus matrix interfaces to the following external buses:ICode bus.This is for instruction and vector fetches from code s

11、pace,it is a 32-bit AHB-Lite bus.DCode bus.This is for data load/stores and debug accesses to code space.it is a 32-bit AHB-Lite bus.System bus.This is for instruction and vector fetches,data LD/ST and debug accesses to system space.This is a 32-bit AHB-Lite bus.PPB.This is for data LD/ST and debug

12、accesses to PPB space.This is a 32-bit APB(v3.0)bus.第11页/共287页Cortex-M3的总结Cortex-M3的特性Processor coreBus matrixThe bus matrix also controls the following:Unaligned accesses.The bus matrix converts unaligned processor accesses into aligned accesses.Bit-banding.The bus matrix converts bit-band alias ac

13、cesses into bit-band region accesses.It performs:bit field extract for bit-band loads;atomic read-modify-write for bit-band stores.Write buffering.The bus matrix contains a one-entry write buffer to decouple bus stalls from the processor core.第12页/共287页Cortex-M3的总结Cortex-M3的特性Processor coreDWTYou ca

14、n configure the implementation to include a DWT.If present,you can configure the DWT to incorporate the following debug functionality:four comparators that you can configure either as a hardware watchpoint,an ETM trigger,a PC sampler event trigger,or a data address sampler event triggerseveral count

15、ers or a data match event trigger for performance profiling(性能分析)configurable to emit PC samples at defined intervals,and to emit interrupt event information.第13页/共287页Cortex-M3的总结Cortex-M3的特性Processor coreETMYou can configure the system at implementation to include an ETM.This is a low-cost trace m

16、acrocell that supports instruction trace only.WICYou can configure the implementation to include a Wake-up Interrupt Controller(WIC).第14页/共287页Cortex-M3的总结Cortex-M3的编程模式About the programmers modelThe processor architecture is the ARMv7-M.Instructions architecture is the Thumb-2.Operating modes：The p

17、rocessor supports two modes of operation,Thread mode and Handler mode:Thread mode is entered on Reset,and can be entered as a result of an exception return.Privileged and User(Unprivileged)code can run in Thread mode.Handler mode is entered as a result of an exception.All code is privileged in Handl

18、er mode.第15页/共287页Cortex-M3的总结Cortex-M3的编程模式About the programmers modelOperating statesThe processor can operate in one of two operating states:Thumb-2 state.This is normal execution running 16-bit and 32-bit halfword aligned Thumb instructions.Debug State.This is the state when in halting debug.第16

19、页/共287页Cortex-M3的总结Cortex-M3的编程模式Privileged access and user accessCode can execute as privileged or user:User(Unprivileged)execution limits or excludes access to some resources.Privileged execution has access to all resources.Handler mode is always privileged.Thread mode can be privileged or unprivi

20、leged.When Thread mode has been changed from privileged to user,it cannot change itself back to privileged.Only a Handler can change the privilege of Thread mode.Handler mode is always privileged.第17页/共287页Cortex-M3的总结Cortex-M3的编程模式Privileged access and user accessMain stack and process stackOut of

21、reset,all code uses the main stack.An exception handler such as SVC can change the stack used by Thread mode from main stack to process stack by changing the EXC_RETURN value it uses on exit.All exceptions continue to use the main stack.The stack pointer,r13,is a banked register that switches betwee

22、n SP_main and SP_process.Only one stack,the process stack or the main stack,is visible,using r13,at any time.It is also possible to switch from main stack to process stack while in Thread mode by writing to CONTROL1 using the MSR instruction,in addition to being selectable using the EXC_RETURN value

23、 from an exit from Handler mode.第18页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersThe processor has the following 32-bit registers:13 general-purpose registers,r0-r12Stack point alias of banked registers,SP_process and SP_mainLink register,r14Program counter,r15One program status register,xPSR.Figure sho

24、ws the processor register set.第19页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersThe processor has the following 32-bit registers:13 general-purpose registers,r0-r12Stack point alias of banked registers,SP_process and SP_mainLink register,r14Program counter,r15One program status register,xPSR.Figure shows

25、 the processor register set.第20页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersGeneral-purpose registersThe general-purpose registers r0-r12 have no special architecturally-defined uses.Most instructions that can specify a general-purpose register can specify r0-r12.Low registers Registers r0-r7 are acces

26、sible by all instructions that specify a general-purpose register.High registers Registers r8-r12 are accessible by all 32-bit instructions that specify a general-purpose register.Registers r8-r12 are not accessible by all 16-bit instructions.第21页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersThe r13 have

27、 following special functions:Stack pointer Register r13 is used as the Stack Pointer(SP).Because the SP ignores writes to bits 1:0,it is autoaligned to a word,four-byte boundary.Handler mode always uses SP_main,but you can configure Thread mode to use either SP_main or SP_process.The r14 have follow

28、ing special functions:Link register Register r14 is the subroutine Link Register(LR).The LR receives the return address from PC when a Branch and Link(BL)or Branch and Link with Exchange(BLX)instruction is executed.第22页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersThe r14 have following special functions

29、:The LR is also used for exception return.At all other times,you can treat r14 as a general-purpose register.The r15 have following special functions:Program counter Register r15 is the Program Counter(PC).Bit 0 is always 0,so instructions are always aligned to word or halfword boundaries.第23页/共287页

30、Cortex-M3的总结Cortex-M3的编程模式RegistersSpecial-purpose Program Status Registers(xPSR)Processor status at the system level breaks down into three categories:Application PSRInterrupt PSRExecution PSRThey can be accessed as individual registers,a combination of any two from three,or a combination of all th

31、ree using the Move to Register from Status(MRS)and MSR instructions.第24页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersSpecial-purpose Program Status Registers(xPSR)Application PSRThe Application PSR(APSR)contains the condition code flags.Before entering an exception,the processor saves the condition code

32、 flags on the stack.You can access the APSR with the MSR(2)and MRS(2)instructions.Figure shows the bit assignments of the APSR.第25页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersxPSR APSR第26页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersxPSRInterrupt PSRThe Interrupt PSR(IPSR)contains the Interrupt Service Rou

33、tine(ISR)number of the current exception activation.第27页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersxPSR IPSR第28页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersxPSR Execution PSRThe Execution PSR(EPSR)contains two overlapping fields:the Interruptible-Continuable Instruction(ICI)field for interrupted load mul

34、tiple and store multiple instructions;the execution state field for the If-Then(IT)instruction,and the Thumb state bit(T-bit).Interruptible-continuable instruction field.Load Multiple(LDM)operations and Store Multiple(STM)operations are interruptible.The ICI field of the EPSR holds the information r

35、equired to continue the load or store multiple from the point that the interrupt occurred.第29页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersxPSR Execution PSRIf-then state field:The IT field of the EPSR contain the execution state bits for the If-Then instruction.Because the ICI field and the IT field ov

36、erlap,load or store multiples within an If-Then block cannot be interrupt-continued.第30页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersxPSR EPSR第31页/共287页Cortex-M3的总结Cortex-M3的编程模式RegistersSaved xPSR bitsOn entering an exception,the processor saves the combined information from the three status registers

37、on the stack.The stacked xPSR also contains information about whether the stack was 8-byte aligned or not depending on the value of STKALIGN in the Configuration Control Register.This information is stored in bit 9 of the xPSR on the stack,and it is a 1 if the stack was forced to be 8-byte aligned.第

38、32页/共287页Cortex-M3的总结Cortex-M3的编程模式Memory formatsThe processor views memory as a linear collection of bytes numbered in ascending order from 0.For example:bytes 0-3 hold the first stored wordbytes 4-7 hold the second stored word.The processor can access data words in memory in little-endian format o

39、r big-endian format.It always accesses code in little-endian format.第33页/共287页Cortex-M3的总结Cortex-M3的编程模式Memory formatslittle-endian format第34页/共287页Cortex-M3的总结Cortex-M3的编程模式Instruction set summaryThis section provides:a summary of the processor 16-bit instructionsa summary of the processor 32-bit i

40、nstructions.略第35页/共287页Cortex-M3的总结System ControlSummary of processor registersDescribes the registers that control functionality.It contains the following:Nested Vectored Interrupt Controller registersCore debug registers;System debug registers;Debug interface port registers;Memory Protection Unit

41、registers;Trace Port Interface Unit registers;Embedded Trace Macrocell registers.第36页/共287页Cortex-M3的总结System ControlSummary of processor registersDescribes the registers that control functionality.It contains the following:Nested Vectored Interrupt Controller registersCore debug registers;System de

42、bug registers;Debug interface port registers;Memory Protection Unit registers;Trace Port Interface Unit registers;Embedded Trace Macrocell registers.主要介绍NVIC第37页/共287页Cortex-M3的总结NVICNVIC register mapThe NVIC space is split as follows:0 xE000E000-0 xE000E00F:Interrupt Type Register0 xE000E010-0 xE00

43、0E0FF:System Timer0 xE000E100-0 xE000ECFF:NVIC0 xE000ED00-0 xE000ED8F:System Control Block:CPUID System control,configuration,and status Fault reporting0 xE000EF00-0 xE000EF0F:Software Trigger Exception Register0 xE000EFD0-0 xE000EFFF:ID space.第38页/共287页Cortex-M3的总结NVICName of registerTypeAddressRes

44、et valueInterrupt Control Type RegisterRead-only0 xE000E004 aAuxiliary Control RegisterRead/write0 xE000E008 0 x0SysTick Control and Status RegisterRead/write0 xE000E010 0 x00000000SysTick Reload Value RegisterRead/write0 xE000E014 UnpredictableSysTick Current Value RegisterRead/write clear 0 xE000E

45、018 UnpredictableSysTick Calibration Value RegisterRead-only0 xE000E01C STCALIBIrq 0 to 31 Set Enable RegisterRead/write0 xE000E100 0 x00000000.Irq 224 to 239 Set Enable RegisterRead/write0 xE000E11C 0 x00000000Irq 0 to 31 Clear Enable RegisterRead/write0 xE000E180 0 x00000000.Irq 224 to 239 Clear E

46、nable RegisterRead/write0 xE000E19C 0 x00000000Irq 0 to 31 Set Pending RegisterRead/write0 xE000E200 0 x00000000.Irq 224 to 239 Set Pending RegisterRead/write0 xE000E21C 0 x00000000Irq 0 to 31 Clear Pending RegisterRead/write0 xE000E280 0 x00000000.Irq 224 to 239 Clear Pending Register Read/write0 x

47、E000E29C 0 x00000000Irq 0 to 31 Active Bit RegisterRead-only0 xE000E300 0 x00000000.Irq 224 to 239 Active Bit RegisterRead-only0 xE000E31C 0 x00000000第39页/共287页Cortex-M3的总结NVICName of registerTypeAddressReset valueIrq 0 to 3 Priority RegisterRead/write0 xE000E4000 x00000000.Irq 236 to 239 Priority R

48、egisterRead/write0 xE000E4EC 0 x00000000CPUID Base RegisterRead-only0 xE000ED000 x412FC230Interrupt Control State RegisterRead/write or read-only 0 xE000ED040 x00000000Vector Table Offset RegisterRead/write0 xE000ED080 x00000000Application Interrupt/Reset Control Register Read/write0 xE000ED0C 0 x00

49、000000System Control RegisterRead/write0 xE000ED100 x00000000Configuration Control RegisterRead/write0 xE000ED140 x00000200System Handlers 4-7 Priority RegisterRead/write0 xE000ED180 x00000000System Handlers 8-11 Priority RegisterRead/write0 xE000ED1C 0 x00000000System Handlers 12-15 Priority Regist

50、erRead/write0 xE000ED200 x00000000System Handler Control and State RegisterRead/write0 xE000ED240 x00000000Configurable Fault Status RegistersRead/write0 xE000ED280 x00000000Hard Fault Status RegisterRead/write0 xE000ED2C 0 x00000000Debug Fault Status RegisterRead/write0 xE000ED300 x00000000Mem Mana