数字电路英文版第五单元.pptx

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1、CHAPTER 5 Dual symbol (对偶符号)Node (节点)Signal tracing(信号跟踪)Universal gate (万能门)Combinational logic (组合逻辑)Sequential logic(时序逻辑)第1页/共74页KAY TERMDual symbols The negative-AND is the dual symbol for the NOR gate,and the negative-OR is the dual symbol fot the NAND gate.Node A common connection point in a

2、circuit in which a gate output is connected to one or more gate inputs.第2页/共74页Signal tracing A troubleshooting technique in which waveforms are observed in a step-by-step manner beginning at the input and working toward the output or vice versa.At each point the observed waveform is compared with t

3、he correct signal for that point.第3页/共74页Universal gate Either a NAND gate or a NOR gate.The term universal refers to the property of a gate that permits any logic function to be implemented by that gate or by a combination of gates of that kind.第4页/共74页 5.1 BASIC COMBINATIONAL LOGIC CIRCUITS In Cha

4、pter 4,you learned that SOP expressions are implemented with an AND gate for each product term and one OR gate for summing all of the product terms.This SOP implementation is called ANDOR logic and is the basic form for realizing standard Boolean functions.2.第5页/共74页In this section,the ANDOR and the

5、 AND-OR-Invert are examined;and the exclusive-OR and exclusive-NOR gates,which are actually a form of AND-OR logic,are covered.3.第6页/共74页AND-OR Logic (SOP)ABDCABXCD&1ABCDXX=AB+CD4.Fig.5-1第7页/共74页 Input Output A B C D AB CD X 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 1 0

6、 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1TABLE 5-1Truth table for the AND-OR logic in Fig.5-15.X=AB+CD第8页/共74页AND-OR-Invert Logic (POS)ABDCABXCD&1ABCDXX=AB+CD=(A+B)(C+D)6.第9页/共74页ABXExclusive-O

7、R LogicABXX=AB+AB =A BABX=17.ABAB第10页/共74页 Input OutputA B X 0 0 0 0 1 1 1 0 1 1 1 08.X=AB+AB =A B第11页/共74页ABXExclusive-NOR LogicXORABXX=AB+ABX=AB+ABABAB9.第12页/共74页ABXX=1X=AB+AB =AB+AB =A B10.第13页/共74页 5.2 IMPLEMENTING COMBINATIONAL LOGICIn this section,examples are used to illustrate how to impleme

8、nt a logic circuit from a Boolean expression or a truth table.Minimization of a logic circuit using the methods covered in Chapter 4 is also discussed.11.第14页/共74页From a Boolean Expression to a Logic CircuitLets examine the following Boolean expression:X=AB+CDEANDORX=AB+CDEABCDE12.第15页/共74页As anothe

9、r example,lets implement the following expression:X=AB(CD+EF)ANDNOTORANDABCDEFCDEFDCD+EFX=AB(CD+EF)13.(a)第16页/共74页X=AB(CD+EF)=ABCD+ABEFABCDABEFDABCEF X=ABCD+ABEF(Sum-of-products implementation of circuit in part(a).)14.第17页/共74页From a Truth Table to a Logic Circuit Input OutputA B C X 0 0 0 0 0 0 1

10、0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0ABCABCX=ABC+ABC15.第18页/共74页X=ABC+ABCXABCABCAABBCC16.第19页/共74页 5.3 THE UNIVERSAL PROPERTY OF NAND AND NOR GATES Up to this point,combinational circuits implemented with AND gates,OR gates,and inverters have been studied.In this section,the universal pr

11、operty of the NAND gate and the NOR gate is discussed.17.第20页/共74页The universality of the NAND gate means that it can be used as an inverter and that combinations of NAND gates can be used to implement the AND,OR,and NOR operations.Similarly,the NOR gate can be used to implement the inverter,AND,OR,

12、and NAND operation.18.第21页/共74页The NAND Gate as a Universal Logic ElementBBAAAAAABAB=ABABA(a)A NAND gate used as an inverter(b)Two NAND gate used as an AND gate19.第22页/共74页A B=A+BAABBABA+B(c)Three NAND gate used as an OR gateAABBABA+BA+BAB=A+B(d)Four NAND gate used as an NOR gateG1G2G3G1G2G3G420.第23

13、页/共74页The NOR Gate as a Universal Logic ElementBBAAAAAA+BA+BA+BA(a)A NOR gate used as an inverter(b)Two NOR gate used as an OR gate21.第24页/共74页A+B=ABAABBAB(c)Three NOR gate used as an AND gateABABA BAB(d)Four NOR gate used as an NAND gateABA BABG1G2G3G1G2G3G422.第25页/共74页 5.4 COMBINATIONAL LOGIC USIN

14、G NAND AND NOR GATES In this section,you will see how NAND and NOR gates can be used to implement a logic function.Recall from Chapter 3 that the NAND gate also exhibits an equivalent operation called the negative-OR and that the NOR gate exhibits an equivalent operation called the negative-AND.23.第

15、26页/共74页You will see how the use of the appropriate symbols to represent the equivalent operations makes “reading”a logic diagram easier.24.第27页/共74页NAND LogicAB=A+BX=(A B)(C D)=(A+B)(C+D)=(A+B)+(C+D)=A B+C D =A B+C DBAABCDCDX=AB+CDNANDnegative-OR25.第28页/共74页BACDX=AB+CDG2 acts as ANDG1 acts as ORG3

16、acts as ANDBACDBACDAB+CDAB+CDBubbles cancelBubbles cancel26.第29页/共74页NAND Logic DiagramsAABBCCDDEFEF(AB+C)D+EFXX=ABCD EF =ABCD+EF =(AB+C)D+EF =(AB+C)D+EFABAB+C(AB+C)DEFABABCABCDEFBubbles cancels barBubbles adds bar to CBubbles cancels barORANDORAND27.第30页/共74页NOR LogicA+B=A BX=A+B+C+D =(A+B)(C+D)=(A

17、+B)(C+D)C+DNORnegative-ANDCDAB28.A+B第31页/共74页BACDX=(A+B)(C+D)G2 acts as ORG1 acts as ANDG3 acts as ORBACDX=(A+B)(C+D)Bubbles cancelBubbles cancel29.A+B=A B第32页/共74页NOR Logic DiagramsAABBCCDDEFEF(A+B)C+D(E+F)X=A+B+C+D+E+F =(A+B+C+D)(E+F)=(A+B)C+D)(E+F)=(A+B)C+D)(E+F)A+B(A+B)C(A+B)C+DE+FA+BA+B+CA+B+C+

18、DE+FBubbles cancels barBubbles adds bar to CBubbles cancels barANDORANDOR30.第33页/共74页 5.5 OPERATION WITH PULSE WAVEFORMS Several examples of general combinational logical circuits with pulse waveform inputs are examined in this section.Keep in mind that the logical operation of each gate is the same

19、 for pulse inputs as for constantlevel inputs.31.第34页/共74页The output of a logic circuit at any given time depends on the inputs at that particular time,so the relationship of the time-varying inputs is of primary importance.32.第35页/共74页1.The output of an AND gate is HIGH only when all inputs are HIG

20、H at the same time.2.The output of an OR gate is HIGH only when at least one of its inputs is HIGH.3.The output of a NAND gate is LOW only when all inputs are HIGH at the same time.4.The output of an NOR gate is LOW only when at least one of its inputs is HIGH.33.第36页/共74页EXAMPLE 511.Showing the out

21、puts of G1,G2,and G3 with input waveforms,A and B,as indicated.ABG1G2G3X=AB+AB34.第37页/共74页FIGURE 5-33ABXG2 output=ABG3 output=AB35.X=AB+AB第38页/共74页EXAMPLE 512.Determine the outputs waveforms X for the logic circuit as follow:ABCDX=Y3+Y4=Y1C+Y2D=(A+B)C+CD=AC+BC+CDY1=A+BY3=Y1CY2=CY4=Y2D36.第39页/共74页BAC

22、DX37.Y1=A+BY2=CY3=Y1CY4=Y2D=AC+BC+CDACACCDBC第40页/共74页Using K-maps to Eliminate Timing HazardsAL=A AAAAL第41页/共74页AALBCCACBCCBACBCLL=AC+BC第42页/共74页 ABC000111100 1 1 1 1 1L=AC+BC+AB (111 110)ACBACBCLAB第43页/共74页00000AB0000010111111010CD0000(A+C)(B+C)(A+C+D)(A+B+D)ACBCACDACBCACDABDLL第44页/共74页Chapter 5:Co

23、mbinational LogicTrue/False1.The NAND gate is an example of combinational logic.2.Fig.5-1 is an example of the implementation of AND-OR-INVERTER logic.ABCDX38.第45页/共74页3.The abbreviation for an exclusive-OR gate is XOR.4.X=ABC+BCD is in the form of a sum-of products expression.5.The K-map in Fig.5-2

24、 shows the correct implementation of the expression,X=ACD+AB(CD+BC).A BA BA BA BC DC DC DC D000000000000111139.第46页/共74页6.NAND gates cannot be used to construct NOR gates.7.NOR gates can be used to construct AND gates.8.The expressions,AB and A+B,are equivalent.9.The effect of an inverted output bei

25、ng connected to the inverting input of another gate is to effectively eliminate one of the inversions,resulting in a single inversion.40.第47页/共74页10.The logic circuit and associated waveforms shown in Fig.5-3 are correct.ABCXABCX41.第48页/共74页Multiple Choice11.Which figure in Fig.5-4 represents AND-OR

26、 logic?BACDXABCXACXABCXBa.b.c.d.&142.第49页/共74页12.Which of the figures in Fig.5-5(a-d)is equivalent to Fig.5-5(e)?ABCDABCDABCDABCDABCDXXXXXa.b.c.d.e.43.第50页/共74页13.Which of the figures in Fig.5-6(a-d)is equivalent to Fig.5-5(e)?ABABABXXXa.b.d.e.Xc.44.第51页/共74页14.Which of the following logic expressio

27、ns represents the logic diagram in Fig.5-7?a.X=AB+AB b.X=AB+ABc.X=AB+AB d.X=AB+ABABX45.第52页/共74页15.What type of logic circuit is represented by Fig.5-7?a.XOR b.XNOR c.XAND d.XNAND46.第53页/共74页16.The logic expressions for in Fig.5-8 is?a.X=ABC+ACD b.X=(AB)(ACCD)c.X=(AB)(AC+CD)d.X=ABC(CBD)ABCDX47.第54页/

28、共74页17.The expended expressions for in Fig.5-8 is?a.X=A(BC+CD)b.X=ACD+ABCD+ABCc.X=ABC+BCDd.X=AABCD+AABCD+ABCD48.第55页/共74页18.Use Boolean algebra to determine the simplest output equation for Fig.5-8.(note:The instructor may require you to show your work for this problem.)a.X=ABCDb.X=A(BC+CD)c.X=ABC+B

29、CDd.X=A(BCD)49.第56页/共74页19.Use K-map to determine the simplest output equation for Fig.5-8.(note:The instructor may require you to show your work for this problem.)a.X=ABCDb.X=A(BC+CD)c.X=ABC+BCDd.X=A(BCD)50.第57页/共74页20.Which circuit in Fig.5-9 implements the equation,X=AB+AC+ABC?ABCABCABCABCABCABCB

30、CAXXXXa.b.c.d.51.第58页/共74页22.How many gates,including inverters,are required to implement the equation,X=ACD+AB(CD+BC),before simplification?a.5 b.9 c.7 d.323.How many gates,including inverters,are required to implement the equation,X=ACD+AB(CD+BC),after simplification with algebra?a.5 b.9 c.7 d.353

31、.第59页/共74页24.How many gates,including inverters,are required to implement the equation,X=ACD+AB(CD+BC),after simplification with a K-map?a.5 b.9 c.7 d.354.第60页/共74页25.The NAND gate is referred to as a“universal”gate,because it .a.Can be found in almost all digital circuits.b.Can be used to build all

32、 the other types of gates.c.Is used in all the countries of the world.d.Was the first gate to be integrated.55.第61页/共74页26.Which of the figures in Fig.5-11(a-d)represents the NAND implementation of a NOR gate?a.c.b.d.56.第62页/共74页27.Which of the figures in Fig.5-11(a-d)represents the NAND implementat

33、ion of an OR gate?28.Which of the figures in Fig.5-11(a-d)represents the NAND implementation of an INVERTER gate?57.第63页/共74页29.The relationship between a NAND gate and a negative-OR gate is expressed by =.a.AB=A+B b.A+B=A+Bc.AB=A+B d.AB=A+B58.第64页/共74页30.Which of the figures in Fig.5-12(a-d)is the

34、logical equivalent of Fig.5-12(e)?a.b.c.d.e.59.第65页/共74页31.When the inverted output of the gate is connected to the inverted input of another gate,.a.the inversions cancel.b.a double inversion occurs and the signal is inverted.c.one inversion cancels the other and only a single inversion results.d.A

35、ll of the above are correct.60.第66页/共74页32.Why are multiple NAND gates used to replace other single function gates?a.It is easier to design logic circuits with a single gate type,since you only have to fully understand how one type of gate works.b.NAND gates are cheaper than any other type of gate.c

36、.NAND gates are packaged more densely on ICs than other types of gates.d.It makes it possible to use spare portions of NAND IC packages to implement other logic functions,perhaps reducing the total IC package count.61.第67页/共74页33.Which of the figures in Fig.5-13(a-d)is the correct NAND logic impleme

37、ntation of the expression,X=ABC+DE?a.b.c.d.ABCDEXXXXABCDEABCDEABCDE62.第68页/共74页34.The relationship between a NOR gate and a negative-AND gate is expressed by =.a.A+B=ABb.A+B=A+Bc.AB=A+Bd.AB=A+B63.第69页/共74页35.Which of the figures in Fig.5-14(a-d)represents the NOR implementation of an OR gate?a.c.b.d

38、.64.第70页/共74页36.Which of the figures in Fig.5-14(a-d)represents the NOR implementation of an AND gate?37.Which of the figures in Fig.5-14(a-d)represents the NOR implementation of an NAND gate?65.第71页/共74页38.The reason that NOR logic networks are redrawn,as in Fig.5-15,is .a.To minimize the number of

39、 parts required.b.To make it easier to determine the logical output.c.That it shows the actual gate arrangement.d.To help make the transition to a K-map.ABCDX66.第72页/共74页39.Which of the waveforms in Fig.5-16(a-d)shows the correct output for the circuit in Fig.5-16?ABCabcdABCX67.END第73页/共74页感谢您的观看。第74页/共74页