数字电路英文版第三单元.pptx

《数字电路英文版第三单元.pptx》由会员分享，可在线阅读，更多相关《数字电路英文版第三单元.pptx（116页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、 CHAPTER 3 AND gate (与门)ANSI (美国国家标准协会)Boolean addition (布尔加 )Boolean algebra (布尔代数)Boolean multiplication (布尔乘)ECL (射极偶合逻辑)CMOS (互补金属氧化物半导体)Enable (使能端)Complementation (取反)Inversion (反)Exclusive-NOR(XNOR)gate (异或非门)Exclusive-OR(XOR)gate (异或门)2.第1页/共116页Fan-out (扇出)IEEE (电气和电子工程师协会)NAND gate(与非门)Neg

2、ative-AND (负与门)Negative-OR gate (负或门)NOR gate (或非门)OR gate (或门)Power dissipation (功耗)Propagation delay time(延迟时间)Truth table (真值表)Speed-power product (速度功率积)Unit load (单位负载)TTL (晶体管-晶体管逻辑)3.第2页/共116页KEY TERMSAND gate A logic gate that produces a high output only when all of the inputs are HIGH.ANSI

3、American National Standards Institute.Bollean addition In Boolean algebra,the OR operation.第3页/共116页Boolean algebra The mathematics of logic circuits.CMOS Complementary metal-oxide semiconductor;a class of integrated logic that is implemented with a type of field-effect transistor.Complementation In

4、version.LOW is the complement of HIGH,and 0 is the complement of 1.第4页/共116页ECL Emitter-coupled logic;a class of integrated logic circuit that is implemented with nonsaturating bipolar junction transistors.Enable To active or put into an operational mode;an input on a logic circuit that enable its o

5、peration.第5页/共116页Exclusive-NOR(XNOR)gateA logic gate that produces a LOW output only when its two inputs are at oppsite levels.Exclusive-OR(XOR)gateA logic gate that produces a HIGH output only when its two inputs are at oppsite levels.第6页/共116页Fan-out The number of equivalent gate inputs of the sa

6、me family series that a logic gate can drive.IEEE Institute of Electrical and Electronic EngineersNAND gate A logic gate that produces a LOW output only when all of the inputs are HIGH.第7页/共116页Negative-AND An equivalent NOR gate operation in which the HIGH is the active output when all inputs are L

7、OW.Negative-OR An equivalent NAND gate operation in which the HIGH is the active output when one or more of the inputs are LOW.第8页/共116页NOR gate A logic gate in which the output is LOW when one or more of the inputs are HIGH.OR gate A logic gate that produces a HIGH output when one or more of the in

8、puts are HIGH.第9页/共116页Power dissipation The product of the dc supply voltage and the dc supply current in an electronic circuit;the amount of power required by a circuit.Propagation delay time The time interval between the occurrence of an input transition and the occurrence of the corresponding ou

9、tput transition in a logic circuit.第10页/共116页Speed-power product A performance parameter that is the product of the propagation delay time and the power dissipation in a logic circuit.Truth table A table showing the inputs and corresponding output(s)of a logic circuit.第11页/共116页TTL Transistor-transi

10、stor logic;a class of integrated logic circuit that uses bipolar junction transistors.Unit load A measure of fan-out.One gate input represents one unit load to the output of a gate within the same IC family.第12页/共116页The inverter (NOT circuit)performs the operation called inversion or complementatio

11、n.The inverter changes one logic level to the opposite level.In terms of bits,it changes a 1 to 0 and a 0 to 1.(Traditional logic Gate Symbol)3.1 THE INVERTER 4.第13页/共116页(ANSI/IEEE Logic Gate Symbol)A Rin(input)X (output)+5v R(NOT Gate A logic gate with only one input and one output that will inver

12、t the binary input.)115.第14页/共116页Inverter Truth Table Input Output LOW(0)HIGH(1)HIGH(1)LOW(0)Inverter OperationHIGH(1)LOW(0)HIGH(1)LOW(0)t1 t2Input pulse t1 t2Output pulse6.第15页/共116页Timing DiagramsRecall from Chapter 1 that a timing diagram is a graph that accurately displays the relationship of t

13、wo or more waveforms with respect to each other on a time basis.Inputoutput t1 t2Timing diagram For the above Fig.7.第16页/共116页Logic Expression for the Inverter X=A (X equals not A.)AX=AThe inverter complements an input variable.8.第17页/共116页The AND gate is one of the basic gates from which all logic

14、functions are constructed.An AND gate can have two or more inputs and performs what is known as logical multiplication.The term gate is used to describe a circuit that performs a basic logic operation.3.2 THE AND GATE 9.第18页/共116页ABXXABLogical Operation of the AND Gate The AND gate produces a HIGH o

15、utput only when all of the inputs are HIGH.When any of the inputs is LOW,the output is LOW.The gate operation can be stated as follows:For a 2-input AND gate,output X is HIGH if inputs A and B are HIGH;X is LOW if either A or B is LOW,or if both A and B are LOW.&10.第19页/共116页AND Gate Truth Table Inp

16、ut OutputA B X 0 0 0 0 1 0 1 0 0 1 1 111.For any AND gate,regardless of the number of inputs,the output is HIGH only when all inputs are HIGH.第20页/共116页Pulsed OperationABX10110t11111000001t2t3t4t5ABX12.第21页/共116页Logic Expression for the AND GateBoolean multiplication0 0=00 1=01 0=01 1=1Boolean multi

17、plication is the same as the AND function.13.第22页/共116页X=AB (X equals A and B)14.ABX=ABABX=ABCACX=ABCDCBD第23页/共116页Application ExamplesThe AND Gate as an Enable/Inhibit deviceCOUNTERCLOCKDECODER AND DISPLAYRESETINA151S1S第24页/共116页ALARMCIRCUIT 30S TIMERIGNITIONON=HIGHOFF=LOWSEATBELTBUCKLED=LOWUNBUCKL

18、E=HIGH16A Seat Belt Alarm SystemABC第25页/共116页The OR gate is another of the basic gates from which all logic functions are constructed.An OR gate can have two or more inputs and performs what is known as logical addition.1ABXABX 3.3 THE OR GATE 17.第26页/共116页Logic Operation for the OR GateThe OR gate

19、produces a HIGH on the output when any of the inputs is HIGH.The output is LOW only when all of the inputs are LOW.ABXRD2D1ABX5VR18.第27页/共116页OR Gate Truth Table Input OutputA B X 0 0 0 0 1 1 1 0 1 1 1 119.The OR gate produces a HIGH on the output when any of the inputs is HIGH.第28页/共116页Pulsed Oper

20、ationABX1001t110110011t2t3t4ABX20.第29页/共116页Logic Expression for the OR GateBoolean addition0+0=00+1=11+0=11+1=1Boolean addition is the same as the OR function.21.第30页/共116页X=A+B (X equals A or B)ABX=A+BABX=A+B+CACX=A+B+C+DCBD22.第31页/共116页Application ExamplesHIGH=OpenAlarm LOW=ClosecircuitLightOpen

21、door/windowsensor23.第32页/共116页The NAND gate is a popular logic element because it can be used as a universal gate;that is,NAND gates can be used in combination to perform the AND,OR,and inverter operations.The universal property of the NAND gate will be examined thoroughly in Chapter 5.3.4 THE NAND

22、GATE 24.第33页/共116页&ABXXABLogical Operation of the NAND Gate The NAND gate produces a LOW output only when all the inputs are HIGH.When any of the inputs is LOW,the output will be HIGH.The gate operation can be stated as follows:For a 2-input NAND gate,output X is LOW if inputs A and B are HIGH;X is

23、HIGH if either A or B is LOW,or if both A and B are LOW.25.第34页/共116页5VR5VBXANDNOTRRA26.第35页/共116页Truth Table of a 2-input NAND gate.Input OutputA B X 0 0 1 0 1 1 1 0 1 1 1 027.The NAND gate produces a LOW output only when all the inputs are HIGH.第36页/共116页Logic Expression for the NAND GateX=A B (X

24、equals not A and B)=A+B NAND Negative-OR28.Inputs OutputA B AB A+B 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0第37页/共116页 The NOR gate,like the NAND gate,is a useful logic element because it can also be used as a universal gate;that is,NOR gates can be used in combination to perform the AND,OR,and inverter opera

25、tions.The universal property of the NOR gate will be examined thoroughly in Chapter 5.3.5 THE NOR GATE 29.第38页/共116页1XABXLogic Operation for the NOR GateThe NOR gate produces a LOW output when any of its inputs is HIGH.Only when all of its inputs are LOW is the output HIGH.30.第39页/共116页5VR5VABXORNOT

26、RR31.第40页/共116页Truth Table of a 2-input NOR gate.Input OutputA B X 0 0 1 0 1 0 1 0 0 1 1 032.The NOR gate produces a LOW output when any of its the inputs is HIGH.第41页/共116页Pulsed Operation Example 3-14ABXABX33.第42页/共116页 NOR Negative-ANDLogic Expression for the NOR GateX=A+B (X equals not A or B)=A

27、 B34.Inputs OutputA B A+B AB 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 0第43页/共116页Exclusive-OR and exclusive-NOR gates are formed by a combination of other gates already discussed,as you will see in Chapter 5.However,because of their fundamental importance in many applications,these gates are often treated as b

28、asic logic elements with their own unique symbols.3.6 THE EXCLUSIVE-OR AND EXCLUSIVE-NOR GATE 35.第44页/共116页=1ABXABXThe Exclusive-OR Gate A logic gate circuit that will give a HIGH output if any odd number of binary 1s are applied to the input.36.第45页/共116页AB X=AB+AB=A+BABXC?ABA BA B37.第46页/共116页Trut

29、h Table for an exclusive-OR gate.Input OutputA B X Even 0 0 0 Odd 0 1 1 Odd 1 0 1 Even 1 1 038.Odd number of 1s at the input gives a 1 at the output.第47页/共116页List the outputs you would expect for all the possible inputs to three-input exclusive-OR gate.Input Output A B C X Even 0 0 0 0 Odd 0 0 1 1

30、Odd 0 1 0 Even 0 1 1 Odd 1 0 0 Even 1 0 1 Even 1 1 0 Odd 1 1 1 第48页/共116页 Input Output A B C X Even 0 0 0 0 Odd 0 0 1 1 Odd 0 1 0 1 Even 0 1 1 0 Odd 1 0 0 1 Even 1 0 1 0 Even 1 1 0 0 Odd 1 1 1 1 第49页/共116页=1ABXABXThe Exclusive-NOR Gate A NOT-exclusive OR gate that will give a HIGH output if any even

31、 number of binary 1s are applied to the input.39.第50页/共116页AB X=AB+AB=A+BABABAB40.第51页/共116页Truth Table for an exclusive-NOR gate.Input OutputA B X Even 0 0 1 Odd 0 1 0 Odd 1 0 0 Even 1 1 141.Even number of 1s at the input gives a 1 at the output.第52页/共116页Pulsed Operation (exclusive-OR gate)ABX1001

32、t110010011t2t3t4ABX42.第53页/共116页EXAMPLE:what will be the X and Y output from the circuit in Fig if the A and B inputs are either out-of phase or in-phase?ABXA and B=Even,Y=1Yout-of phasein-phaseA and B=Odd,X=1第54页/共116页 3.7 INTEGRATED CIRCUIT LOGIC GATE There are three digital integrated circuit(IC)

33、technologies that are used to implement the basic logic gates.Two of these,CMOS and TTL,are the most widely used and the third,ECL,is used in most specialize applications.43.第55页/共116页CMOS stands for Complementary Metal-Oxide Semiconductor and is implemented with a type of field-effect transistor.TT

34、L stands for Transistor-Transistor Logic and is implemented with bipolar junction transistors.ECL,Emitter-Couple Logic,is also a bipolar technology.44.第56页/共116页CMOS:It appears that CMOS has become the dominant technology and may eventually replace TTL.The prefix 74 indicates commercial grade for ge

35、neral use,and the prefix 54 indicates military grade for more several environments.45.第57页/共116页TTL:It has been and still is a popular digital IC technology.One advantage of TTL is that it is not sensitive to electrostatic discharge as CMOS is and,therefore,is more practical in most laboratory exper

36、imentation and prototyping because you do not have to worry about handling problems.46.第58页/共116页Performance Characteristics and ParametersPropagation Delay TimeDC Supply Voltage(VCC)Power DissipationInput and Output Logic LevelsSpeed-Power Product(SPP)47.第59页/共116页Fan-Out and Loading:The fan-out of

37、 a logic gate is the maximum number of inputs of the same series in an IC family that can be connected to a gates output and still maintain the output voltage levels within specified limits.48.第60页/共116页Unused gate inputs for TTL and CMOS should be be connected to the appropriate logic level.For AND

38、/NAND,it is recommended that unused inputs be connected to VCC and for OR/NOR,unused inputs should be connected to ground.TTLVCCRUnused CMOSVCCCMOS/TTLUnused 49.第61页/共116页 3.8 TROUBLESHOOTINGTroubleshooting is the process of recognizing,isolating,and correcting a fault or failure in a circuit or sys

39、tem.To be an effective troubleshooter,you must understand how the circuit or system is supposed to work and be able to recognize incorrect performance.第62页/共116页For example,to determine whether or not a certain logic gate is faulty,you must know what the output should be for given inputs.At this poi

40、nt it may be helpful to review Section 1-6 on pulsers,probes,and oscilloscopes.第63页/共116页Internal Failure of IC Logic GatesOpens and shorts are the most common types of internal gate failures.These can occur on the inputs or on the output of a gate inside the IC package.Before attempting any trouble

41、shooting,check for proper dc supply voltage and ground.第64页/共116页Effects of an Internally Open InputAn internal open is the result of an open component on the chip or break in the tiny wire connecting the IC chip to the package pin.An open input prevents a pulser signal on that input from getting to

42、 the output of the gate.第65页/共116页Open input No pulses HIGH(a)Pulsing the open input will produce no pulses on the output.Open input(b)Pulsing the good input will produce output pulses for TTL NAND and AND gates because an open input acts as a HIGH.第66页/共116页Conditions for Testing GatesWhen testing

43、a NAND gate or an AND gate,always make sure that the inputs that are not being pulsed are HIGH to enable the gate.When checking a NOR gate or an OR gate,always make sure that the inputs that are not being pulsed are LOW.第67页/共116页Troubleshooting an Open InputTroubleshooting this type of failure is m

44、ost easily accomplished with a logic pulser and probe.(Page 139,FIGURE 3 60)第68页/共116页第69页/共116页(a)(b)(c)(d)(e)(f)AYABABABABABYYYYY第70页/共116页Chapter 3:Logic GatesTrue/False1.A LOW placed on the input of an inverter will produce a HIGH output.2.The symbol shown in fig.3-1 is an AND gate.&50.第71页/共116

45、页3.The input to an AND gate are:A=1,B=0,C=1.The output will be LOW.4.The OR gate performs like two switches wired in series.5.A NAND gate consists of an AND gate and OR gate connected in series with each other.51.第72页/共116页6.The timing diagram for a two input NAND gate is shown in fig.3-2.The gate i

46、s working correctly.IN AIN BOUT X52第73页/共116页7.The truth table shown in Fig.3-3 describe the operation of a NOR gate.Input OutputA B X 0 0 0 0 1 1 1 0 1 1 1 08.The XOR gate will produce an output if only one but not both of the inputs is HIGH.53.第74页/共116页9.TTL stands for transistor-technology-logic

47、.10.The 54 prefix on ICs indicates a broader operating temperature range,generally intended for military use.54.第75页/共116页Multi Choice11.Which of the symbols shown in Fig.3-4 represents an inverter?a b c d&55.第76页/共116页12.The truth table for an inverter is shown in Fig.3-5.For the input conditions s

48、hown,the outputs x and y are and ,respectively.Input Output0 x1 ya.0,0b.1,1c.1,0d.0,156.第77页/共116页13.Which timing diagram shown in fig.3-6 is correct for an inverter?INOUT aOUT bOUT cOUT d57.第78页/共116页14.Which of the symbols shown in Fig.3-7 represents an AND gate?a b c d&58.第79页/共116页15.For the AND

49、 gate truth table shown in Fig.3-8.the values for w,x,y and z and are ,and ,respectively.Input Output 0 0 wa.0,0,0,1b.0,0,1,1c.1,0,0,0d.0,1,0,1 0 1 x 1 0 y 1 1 z59.第80页/共116页16.For a three-input AND gate,with the input waveforms as shown in Fig.3-9,which output waveform is correct?INPUT AINPUT B INP

50、UT COUTPUT aOUTPUT bOUTPUT cOUTPUT d60.第81页/共116页17.Which of the figures in Fig.3-10 represents an OR gate?a b c d&61.第82页/共116页18.For the OR gate truth table shown in Fig.3-11.the values for w,x,y and z and are ,and ,respectively.Input Output 0 0 wa.0,0,0,1b.0,0,1,1c.1,0,0,0d.0,1,1,1 0 1 x 1 0 y 1