51单片机外文原版文献记录资料.doc

《51单片机外文原版文献记录资料.doc》由会员分享，可在线阅读，更多相关《51单片机外文原版文献记录资料.doc（14页珍藏版）》请在淘文阁 - 分享文档赚钱的网站上搜索。

1、TheThe IntroductionIntroduction ofof AT89C51AT89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is com

2、patible with the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer wh

3、ich provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one 5 vector two-level interrupt architecture, a

4、 full duplex serial port, one-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and

5、interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port

6、, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 may also be configured to be the multiplexed address/data bus during accesses to external program and data memory. In this mode P0 has internal Pull-up resistor. Port 0 als

7、o receives the code bytes during Flash programming, and outputs the code bytes during Program verification. External Pull-up resistors are required during Program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal Pull-up resistors. The Port 1 output buffers can sink/source

8、four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal Pull-up resistors and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal Pull-up resistors. Port 1 also receives the low-order ad

9、dress bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal Pull-up resistor and can be used a

10、s inputs. As inputs, Port 2 pins that are externally being pulled low will source current, because of the internal Pull-up resistor. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this app

11、lication, it uses strong internal Pull-up resistor when emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and

12、 verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal Pull-up resistor and can be used as inputs. As inputs, Port 3 pins that ar

13、e externally being pulled low will source current (IIL) because of the Pull-up resistor. Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for

14、 two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at

15、 a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is

16、 active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from ext

17、ernal program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starti

18、ng at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require12-volt

19、VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an

20、 on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal,

21、 since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep

22、 while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when i

23、dle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To

24、eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction

25、 that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not

26、 be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional feature

27、s listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of

28、 EA be in agreement with the current logic level at that pin in order for the device to function properly.译文：译文：AT89C51 的介绍的介绍 描述描述AT89C51 是一个低电压，高性能 CMOS 8 位单片机带有 4K 字节的可反复擦写的程序存储器（PENROM） 。这种器件采用 ATMEL 公司的高密度、不容易丢失存储技术生产，并且能够与 MCS-51 系列的单片机兼容。片内含有 8 位中央处理器和闪烁存储单元，有较强的功能的 AT89C51 单片机能够被应用到控制领域中。功能特

29、性功能特性AT89C51 提供以下的功能标准：4K 字节闪烁存储器，128 字节随机存取数据存储器，32 个 I/O 口，2 个 16 位定时/计数器，1 个 5 向量两级中断结构，1个串行通信口，片内震荡器和时钟电路。另外，AT89C51 还可以进行 0HZ 的静态逻辑操作，并支持两种软件的节电模式。闲散方式停止中央处理器的工作，能够允许随机存取数据存储器、定时/计数器、串行通信口及中断系统继续工作。掉电方式保存随机存取数据存储器中的内容，但震荡器停止工作并禁止其它所有部件的工作直到下一个复位。引脚描述引脚描述VCC：电源电压 GND：地P0 口口P0 口是一组 8 位漏极开路双向 I/O

30、口，即地址/数据总线复用口。作为输出口时，每一个管脚都能够驱动 8 个 TTL 电路。当“1”被写入 P0 口时，每个管脚都能够作为高阻抗输入端。P0 口还能够在访问外部数据存储器或程序存储器时，转换地址和数据总线复用，并在这时激活内部的上拉电阻。P0 口在闪烁编程时，P0 口接收指令，在程序校验时，输出指令，需要接电阻。P1 口口P1 口一个带内部上拉电阻的 8 位双向 I/O 口，P1 的输出缓冲级可驱动 4个 TTL 电路。对端口写“1”，通过内部的电阻把端口拉到高电平，此时可作为输入口。因为内部有电阻，某个引脚被外部信号拉低时输出一个电流。闪烁编程时和程序校验时，P1 口接收低 8 位

31、地址。P2 口口P2 口是一个内部带有上拉电阻的 8 位双向 I/O 口，P2 的输出缓冲级可驱动4 个 TTL 电路。对端口写“1”，通过内部的电阻把端口拉到高电平，此时，可作为输入口。因为内部有电阻，某个引脚被外部信号拉低时会输出一个电流。在访问外部程序存储器或 16 位地址的外部数据存储器时，P2 口送出高 8 位地址数据。在访问 8 位地址的外部数据存储器时，P2 口线上的内容在整个运行期间不变。闪烁编程或校验时，P2 口接收高位地址和其它控制信号。P3 口口P3 口是一组带有内部电阻的 8 位双向 I/O 口，P3 口输出缓冲故可驱动 4个 TTL 电路。对 P3 口写如“1”时，它

32、们被内部电阻拉到高电平并可作为输入端时，被外部拉低的 P3 口将用电阻输出电流。P3 口除了作为一般的 I/O 口外，更重要的用途是它的第二功能，如下表所示：端口引脚第二功能P3.0RXDP3.1TXDP3.2INT0P3.3INT1P3.4T0P3.5T1P3.6WRP3.7RDP3 口还接收一些用于闪烁存储器编程和程序校验的控制信号。RST复位输入。当震荡器工作时，RET 引脚出现两个机器周期以上的高电平将使单片机复位。ALE/ PROG当访问外部程序存储器或数据存储器时，ALE 输出脉冲用于锁存地址的低8 位字节。即使不访问外部存储器，ALE 以时钟震荡频率的 1/16 输出固定的正脉冲

33、信号，因此它可对输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个 ALE 脉冲时，闪烁存储器编程时，这个引脚还用于输入编程脉冲。如果必要，可对特殊寄存器区中的 8EH 单元的 D0 位置禁止 ALE操作。这个位置后只有一条 MOVX 和 MOVC 指令 ALE 才会被应用。此外，这个引脚会微弱拉高，单片机执行外部程序时，应设置 ALE 无效。PSEN程序储存允许输出是外部程序存储器的读选通信号，当 AT89C51 由外部程序存储器读取指令时，每个机器周期两次 PSEN 有效，即输出两个脉冲。在此期间，当访问外部数据存储器时，这两次有效的 PSEN 信号不出现。EA/VPP

34、外部访问允许。欲使中央处理器仅访问外部程序存储器，EA 端必须保持低电平。需要注意的是：如果加密位 LBI 被编程，复位时内部会锁存 EA 端状态。如 EA 端为高电平，CPU 则执行内部程序存储器中的指令。闪烁存储器编程时，该引脚加上+12V 的编程允许电压 VPP，当然这必须是该器件是使用 12V 编程电压 VPP。XTAL1：震荡器反相放大器及内部时钟发生器的输入端。XTAL2：震荡器反相放大器的输出端。时钟震荡器时钟震荡器AT89C51 中有一个用于构成内部震荡器的高增益反相放大器，引脚 XTAL1和 XTAL2 分别是该放大器的输入端和输出端。这个放大器与作为反馈元件的片外石英晶体或

35、陶瓷谐振器一起构成自然震荡器。 外接石英晶体及电容 C1，C2接在放大器的反馈回路中构成并联震荡电路。对外接电容 C1，C2 虽然没有十分严格的要求，但电容容量的大小会轻微影响震荡频率的高低、震荡器工作的稳定性、起振的难易程序及温度稳定性。如果使用石英晶体，我们推荐电容使用30PF10PF，而如果使用陶瓷振荡器建议选择 40PF10PF。用户也可以采用外部时钟。采用外部时钟的电路如图示。这种情况下，外部时钟脉冲接到 XTAL1 端，即内部时钟发生器的输入端，XTAL2 则悬空。由于外部时钟信号是通过一个 2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但最小高电平持续

36、时间和最大的低电平持续时间应符合产品技术条件的要求。内部振荡电路外部振荡电路闲散节电模式闲散节电模式AT89C51 有两种可用软件编程的省电模式，它们是闲散模式和掉电工作模式。这两种方式是控制专用寄存器 PCON 中的 PD 和 IDL 位来实现的。PD 是掉电模式，当 PD=1 时，激活掉电工作模式，单片机进入掉电工作状态。IDL 是闲散等待方式，当 IDL=1，激活闲散工作状态，单片机进入睡眠状态。如需要同时进入两种工作模式，即 PD 和 IDL 同时为 1，则先激活掉电模式。在闲散工作模式状态，中央处理器 CPU 保持睡眠状态，而所有片内的外设仍保持激活状态，这种方式由软件产生。此时，片

37、内随机存取数据存储器和所有特殊功能寄存器的内容保持不变。闲散模式可由任何允许的中断请求或硬件复位终止。终止闲散工作模式的方法有两种，一是任何一条被允许中断的事件被激活，IDL 被硬件清除，即刻终止闲散工作模式。程序会首先影响中断，进入中断服务程序，执行完中断服务程序，并紧随 RETI 指令后，下一条要执行的指令就是使单片机进入闲散工作模式，那条指令后面的一条指令。二是通过硬件复位也可将闲散工作模式终止。需要注意的是：当由硬件复位来终止闲散工作模式时，中央处理器 CPU 通常是从激活空闲模式那条指令的下一条开始继续执行程序的，要完成内部复位操作，硬件复位脉冲要保持两个机器周期有效，在这种情况下，

38、内部禁止中央处理器 CPU 访问片内 RAM，而允许访问其他端口，为了避免可能对端口产生的意外写入：激活闲散模式的那条指令后面的一条指令不应是一条对端口或外部存储器的写入指令。掉电模式掉电模式在掉电模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内 RAM 和特殊功能寄存器的内容在中指掉电模式前被冻结。退出掉电模式的唯一方法是硬件复位，复位后将从新定义全部特殊功能寄存器但不改变 RAM 中的内容，在 VCC 恢复到正常工作电平前，复位应无效切必须保持一定时间以使振荡器从新启动并稳定工作。闲散和掉电模式外部引脚状态。模式程序存储器ALEPSEN P0P1P2P3闲散模式内部1

39、1数据数据数据数据闲散模式内部11浮空数据地址数据掉电模式外部00数据数据数据数据掉电模式外部00数据数据数据数据程序存储器的加密程序存储器的加密AT89C51 可使用对芯片上的三个加密位 LB1，LB2，LB3 进行编程（P）或不编程（U）得到如下表所示的功能：程序加密位保护类型1UUU没有程序保护功能2PUU禁止从外部程序存储器中执行 MOVC 指令读取内部程序存储器的内容3PPU除上表功能外，还禁止程序校验4PPP除以上功能外，同时禁止外部执行当 LB1 被编程时，在复位期间，EA 端的电平被锁存，如果单片机上电后一直没 有复位，锁存起来的初始值是一个不确定数，这个不确定数会一直保存到真正 复位位置。为了使单片机正常工作，被锁存的 EA 电平与这个引脚当前辑电平一致。机密位只能通过整片擦除的方法清除。