TDA7492MV使用规格书.pdf

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1、 October 2009Doc ID 16264 Rev 11/2626TDA7492MV50 W mono BTL class-D audio amplifierFeatures?50 W continuous output power:RL=6,THD=10%at VCC=25 V?40 W continuous output power:RL=8,THD=10%at VCC=25 V?Wide range single supply operation(10-26 V)?High efficiency(=90%)?Four selectable,fixed gain settings

2、of nominally 21.6 dB,27.6 dB,31.1 dB and 33.6 dB?Differential inputs minimize common-mode noise?Standby and mute features?Short-circuit protection?Thermal-overload protection?Externally synchronizableDescriptionThe TDA7492MV is a mono BTL class-D audio amplifier with single power supply designed for

3、 home systems and docking stations.Thanks to the high efficiency and an exposed-pad-down(EPD)package no heatsink is required.PowerSSO-36 withexposed pad downTable 1.Device summaryOrder codeOperating temp.rangePackagePackagingTDA7492MV0 to 70 CPowerSSO-36 EPDTubeTDA7492MV13TR0 to 70 CPowerSSO-36 EPDT

4、ape and ContentsTDA7492MV2/26 Doc ID 16264 Rev 1Contents1Device block diagram .52Pin description .62.1Pin out .62.2Pin list.73Electrical specifications.83.1Absolute maximum ratings.83.2Thermal data .83.3Electrical specifications .84Characterization curves.104.1For 6-load.104.2For 8-load.134.3Test bo

5、ard.165Package mechanical data.176Applications information .196.1Applications circuit .196.2Mode selection.206.3Gain setting .216.4Input resistance and capacitance.216.5Internal and external clocks .226.5.1Master mode(internal clock).226.5.2Slave mode(external clock).226.6Output low-pass filter .236

6、.7Protection function .236.8Diagnostic output .247Revision history .25TDA7492MVList of tablesDoc ID 16264 Rev 13/26 List of tablesTable 1.Device summary.1Table 2.Pin description list.7Table 3.Absolute maximum ratings.8Table 4.Thermal data.8Table 5.Electrical specifications.8Table 6.PowerSSO-36 EPD d

7、imensions.18Table 7.Mode settings.20Table 8.Gain settings.21Table 9.How to set up SYNCLK .22Table 10.Document revision history .25 List of figuresTDA7492MV4/26 Doc ID 16264 Rev 1List of figuresFigure 1.Internal block diagram .5Figure 2.Pin connection(top view,PCB view).6Figure 3.Output power vs supp

8、ly voltage.10Figure 4.THD vs output power(1 kHz).10Figure 5.THD vs output power(100 Hz).11Figure 6.THD vs frequency(100 mW).11Figure 7.THD vs frequency .11Figure 8.Frequency response.12Figure 9.FFT(0 dB).12Figure 10.FFT(-60 dB).12Figure 11.Output power vs supply voltage.13Figure 12.THD vs output pow

9、er(1 kHz).13Figure 13.THD vs output power(100 Hz).14Figure 14.THD vs frequency(100 mW).14Figure 15.THD vs frequency .14Figure 16.Frequency response.15Figure 17.FFT(0 dB).15Figure 18.FFT(-60 dB).15Figure 19.Test board layout.16Figure 20.PowerSSO-36 EPD outline drawing .17Figure 21.Applications circui

10、t for class-D amplifier .19Figure 22.Standby and mute circuits.20Figure 23.Turn-on/off sequence for minimizing speaker“pop”.20Figure 24.Device input circuit and frequency response.21Figure 25.Master and slave connection.22Figure 26.Typical LC filter for a 8-speaker.23Figure 27.Typical LC filter for

11、a 4-speaker.23Figure 28.Behavior of pin DIAG for various protection conditions.24TDA7492MVDevice block diagramDoc ID 16264 Rev 15/26 1 Device block diagramFigure 1 shows the block diagram of the TDA7492MV.Figure 1.Internal block diagram Pin descriptionTDA7492MV6/26 Doc ID 16264 Rev 12 Pin descriptio

12、n2.1 Pin outFigure 2.Pin connection(top view,PCB view)123456789101112131415161718363534333231302928272625242322212019SUB_GNDNCNCNCNCNCNCNCNCOUTNOUTNPVCCPVCCPGNDPGNDOUTPOUTPPGNDVSSSVCCVREFSGND2VDDS2GAIN1GAIN0DIAGSGNDVDDSSYNCLKROSCINNINPMUTESTBYVDDPWSVREP,exposed pad downConnect to groundTDA7492MVPin

13、descriptionDoc ID 16264 Rev 17/26 2.2 Pin list Table 2.Pin description listNumberNameTypeDescription1SUB_GNDPOWERConnect to the frame2,3NC-No internal connection4,5NC-No internal connection6,7NC-No internal connection8,9NC-No internal connection10,11OUTNOUTNegative PWM output 12,13PVCCPOWERPower sup

14、ply for output channel14,15PGNDPOWERPower ground for output channel16,17OUTPOUTPositive PWM output18PGNDPOWERPower supply ground19VDDPWOUT3.3-V(nominal)regulator output referred to ground for power stage20STBYINPUTStandby mode control21MUTEINPUTMute mode control 22INPINPUTPositive differential input

15、 23INN INPUTNegative differential input24ROSCOUTMaster oscillator frequency-setting pin25SYNCLCKIN/OUTClock in/out for external oscillator26VDDSOUT3.3-V(nominal)regulator output referred to ground for signal blocks27SGNDPOWERSignal ground28DIAGOUTOpen-drain diagnostic output29SVROUTSupply voltage re

16、jection30GAIN0INPUTGain setting input 131GAIN1INPUTGain setting input 232VDDS2INPUTTo be connected to VDDS(pin 26)33SGND2INPUTTo be connected to SGND(pin 27)34VREFOUTHalf VDDS(nominal)referred to ground35SVCCPOWERSignal power supply36VSSOUT3.3-V(nominal)regulator output referred to power supply-EP-E

17、xposed pad for ground-plane heatsink,to be connected to ground Electrical specificationsTDA7492MV8/26 Doc ID 16264 Rev 13 Electrical specifications3.1 Absolute maximum ratings 3.2 Thermal data 3.3 Electrical specificationsUnless otherwise stated,the results in Table 5 below are given for the conditi

18、ons:VCC=25 V,RL(load)=8,ROSC=R3=39 k,C8=100 nF,f=1 kHz,GV=21.6 dB and Tamb=25 C.Table 3.Absolute maximum ratingsSymbolParameterValueUnitVCCDC supply voltage for pins PVCC,SVCC30VVIVoltage limits for input pins STBY,MUTE,INN,INP,GAIN0,GAIN1-0.3-3.6VTopOperating temperature0 to 70CTjJunction temperatu

19、re-40 to 150CTstgStorage temperature-40 to 150CTable 4.Thermal dataSymbolParameterMinTypMaxUnitRth j-caseThermal resistance,junction to case-23C/WTable 5.Electrical specifications SymbolParameterConditionMinTypMaxUnitVCCSupply voltage for pins PVCCA,PVCCB,SVCC-10-26VIqTotal quiescent currentWithout

20、LC-2635mAIqSTBYQuiescent current in standby-2.55.0AVOSOutput offset voltagePlay mode-100-100mVMute mode-60-60IOCPOvercurrent protection thresholdRL=0 4.86.0-ATjJunction temperature at thermal shutdown-150-CRiInput resistanceDifferential input4860-kVOVPOvervoltage protection threshold-2829-VTDA7492MV

21、Electrical specificationsDoc ID 16264 Rev 19/26 VUVPUndervoltage protection threshold-7VRdsONPower transistor on resistanceHigh side-0.2-Low side-0.2-PoOutput powerTHD=10%-40-WTHD=1%-32-PoOutput power RL=6,THD=10%,VCC=25V-50-WRL=6,THD=1%VCC=25V-40-PDDissipated powerPo=40W,THD=10%-4.0-WEfficiencyPo=4

22、0 W8090-%THDTotal harmonic distortionPo=1 W-0.10.4%GVClosed-loop gainGAIN0=L,GAIN1=L20.621.622.6dBGAIN0=L,GAIN1=H26.627.628.6GAIN0=H,GAIN1=L30.131.132.1GAIN0=H,GAIN1=H32.633.634.6GVGain matching-1-1dBeNTotal input noiseA Curve,GV=20 dB-20-Vf=22 Hz to 22 kHz-2535SVRRSupply voltage rejection ratiofr=1

23、00 Hz,Vr=0.5 V,CSVR=10 F4050-dBTr,TfRise and fall times-50-nsfSWSwitching frequencyInternal oscillator290310330kHzfSWROutput switching frequency rangeWith internal oscillator(1)250-400kHzWith external oscillator(2)250-400VinHDigital input high(H)-2.3-VVinLDigital input low(L)-0.8AMUTEMute attenuatio

24、nVMUTE=1 V 6080-dB1.fSW=106/(16*ROSC+182)*4)kHz,fSYNCLK=2*fSW with R3=39 k(see Figure 21.).2.fSW=fSYNCLK/2 with the frequency of the external oscillator.Table 5.Electrical specifications (continued)SymbolParameterConditionMinTypMaxUnit Characterization curvesTDA7492MV10/26 Doc ID 16264 Rev 14 Charac

25、terization curvesThe following characterization curves were made using the TDA7492MV exposed-pad-down test board with VCC=25 V,a signal frequency of 1 kHz and an output power of 1 W unless otherwise specified.The LC filter for the 8-load uses components of 33 H and 220 nF and for the 6-load 22 H and

26、 220 nF.4.1 For 6-loadFigure 3.Output power vs supply voltage Figure 4.THD vs output power(1 kHz)12162024283236404448521516171819202122232425Supply Voltage(V)Output Power(W)12162024283236404448521516171819202122232425Supply Voltage(V)Output Power(W)THD=10%THD=1%THD vs.Output PowerTHD(%)Output Power(

27、W)0.005100.010.020.050.10.20.5125200m60500m1251020THD vs.Output PowerTHD(%)Output Power(W)0.005100.010.020.050.10.20.5125200m60500m1251020THD vs.Output PowerTHD(%)Output Power(W)0.005100.010.020.050.10.20.5125200m60500m1251020TDA7492MVCharacterization curvesDoc ID 16264 Rev 111/26 Figure 5.THD vs ou

28、tput power(100 Hz)Figure 6.THD vs frequency(100 mW)Figure 7.THD vs frequency THD vs.Output Power0.005100.010.020.050.10.20.5125200m60500m1251020THD(%)Output Power(W)THD vs.Output Power0.005100.010.020.050.10.20.5125200m60500m1251020THD(%)Output Power(W)THD(%)THD vs.FrequencyFrequency(Hz)0.010.50.020

29、.030.040.050.060.080.10.20.30.42020k501002005001k2k5k10kTHD(%)THD vs.FrequencyFrequency(Hz)0.010.50.020.030.040.050.060.080.10.20.30.42020k501002005001k2k5k10kTHD vs.FrequencyFrequency(Hz)0.010.50.020.030.040.050.060.080.10.20.30.42020k501002005001k2k5k10kTHD(%)THD vs.FrequencyFrequency(Hz)0.010.50.

30、020.030.040.050.060.080.10.20.30.42020k501002005001k2k5k10kTHD(%)Characterization curvesTDA7492MV12/26 Doc ID 16264 Rev 1Figure 8.Frequency responseFigure 9.FFT(0 dB)Figure 10.FFT(-60 dB)qypAmpl(dB)Frequency(Hz)-5+2-4-3-2-1-0+11030k20501002005001k2k5k10kqypAmpl(dB)Frequency(Hz)-5+2-4-3-2-1-0+11030k2

31、0501002005001k2k5k10kFrequency(Hz)FFT(0 dB)FFT(dB)-150+10-140-130-120-110-100-90-80-70-60-50-40-30-20-10+02020k501002005001k2k5k10kFrequency(Hz)FFT(0 dB)FFT(dB)-150+10-140-130-120-110-100-90-80-70-60-50-40-30-20-10+02020k501002005001k2k5k10kFrequency(Hz)FFT(dB)FFT(60 dB)-150+0-140-130-120-110-100-90

32、-80-70-60-50-40-30-20-102020k501002005001k2k5k10kFrequency(Hz)FFT(dB)FFT(60 dB)-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-102020k501002005001k2k5k10kTDA7492MVCharacterization curvesDoc ID 16264 Rev 113/26 4.2 For 8-loadFigure 11.Output power vs supply voltage Figure 12.THD vs output power(1

33、kHz)1014182226303438421516171819202122232425Suppl y Vol t age(V)O ut put Pow er(W)THD=10%THD=1%THD vs.Output PowerTHD(%)Output Power(W)0.005100.010.020.050.10.20.5125100m60200m500m1251020THD vs.Output PowerTHD(%)Output Power(W)0.005100.010.020.050.10.20.5125100m60200m500m1251020THD vs.Output PowerTH

34、D(%)Output Power(W)0.005100.010.020.050.10.20.5125100m60200m500m1251020 Characterization curvesTDA7492MV14/26 Doc ID 16264 Rev 1Figure 13.THD vs output power(100 Hz)Figure 14.THD vs frequency(100 mW)Figure 15.THD vs frequency THD vs.Output PowerTHD(%)Output Power(W)0.005100.010.020.050.10.20.5125100

35、m60200m500m1251020THD vs.Output PowerTHD(%)Output Power(W)0.005100.010.020.050.10.20.5125100m60200m500m1251020THD(%)THD vs.FrequencyFrequency(Hz)0.010.50.020.030.040.050.060.080.10.20.30.42020k501002005001k2k5k10kTHD(%)THD vs.FrequencyFrequency(Hz)0.010.50.020.030.040.050.060.080.10.20.30.42020k5010

36、02005001k2k5k10kTHD vs.FrequencyFrequency(Hz)THD(%)0.010.50.020.030.040.050.060.080.10.20.30.42020k501002005001k2k5k10kTHD vs.FrequencyFrequency(Hz)THD(%)0.010.50.020.030.040.050.060.080.10.20.30.42020k501002005001k2k5k10kTDA7492MVCharacterization curvesDoc ID 16264 Rev 115/26 Figure 16.Frequency re

37、sponseFigure 17.FFT(0 dB)Figure 18.FFT(-60 dB)Frequency ResponseAmpl(dB)Frequency(Hz)-5+2-4-3-2-1-0+1r1030k20501002005001k2k5k10kFrequency ResponseAmpl(dB)Frequency(Hz)-5+2-4-3-2-1-0+1r1030k20501002005001k2k5k10kFrequency(Hz)FFT(0 dB)FFT(dB)-150+10-140-130-120-110-100-90-80-70-60-50-40-30-20-10+0202

38、0k501002005001k2k5k10kFrequency(Hz)FFT(0 dB)FFT(dB)-150+10-140-130-120-110-100-90-80-70-60-50-40-30-20-10+02020k501002005001k2k5k10kFrequency(Hz)FFT(0 dB)FFT(dB)-150+10-140-130-120-110-100-90-80-70-60-50-40-30-20-10+02020k501002005001k2k5k10kFrequency(Hz)FFT(dB)FFT(-60 dB)-150+0-140-130-120-110-100-

39、90-80-70-60-50-40-30-20-102020k501002005001k2k5k10kFrequency(Hz)FFT(dB)FFT(-60 dB)-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-102020k501002005001k2k5k10kFFT(dB)FFT(-60 dB)-150+0-140-130-120-110-100-90-80-70-60-50-40-30-20-102020k501002005001k2k5k10k Characterization curvesTDA7492MV16/26 Doc I

40、D 16264 Rev 14.3 Test boardFigure 19.Test board layout TDA7492MVPackage mechanical dataDoc ID 16264 Rev 117/26 5 Package mechanical dataThe TDA7492MV comes in a 36-pin PowerSSO package with exposed pad down.Figure 20 below shows the package outline and Table 6 gives the dimensions.Figure 20.PowerSSO

41、-36 EPD outline drawing h x 45 Package mechanical dataTDA7492MV18/26 Doc ID 16264 Rev 1 In order to meet environmental requirements,ST offers these devices in different grades of ECOPACK packages,depending on their level of environmental compliance.ECOPACK specifications,grade definitions and produc

42、t status are available at:.ECOPACK is an ST trademark.Table 6.PowerSSO-36 EPD dimensionsSymbolDimensions in mmDimensions in inchesMinTypMaxMinTypMaxA2.15-2.470.085-0.097A22.15-2.400.085-0.094a10.00-0.100.000-0.004b0.18-0.360.007-0.014c0.23-0.320.009-0.013D10.10-10.500.398-0.413E7.40-7.600.291-0.299e

43、-0.5-0.020-e3-8.5-0.335-F-2.3-0.091-G-0.10-0.004H10.10-10.500.398-0.413h-0.40-0.016k0-8 degrees0-8 degreesL0.60-1.000.024-0.039M-4.30-0.169-N-10 degrees-10 degreesO-1.20-0.047-Q-0.80-0.031-S-2.90-0.114-T-3.65-0.144-U-1.00-0.039-X4.10-4.700.161-0.185Y6.50-7.100.256-0.280TDA7492MVApplications informat

44、ionDoc ID 16264 Rev 119/26 6 Applications information6.1 Applications circuitFigure 21.Applications circuit for class-D amplifier TDA7492MV Applications informationTDA7492MV20/26 Doc ID 16264 Rev 16.2 Mode selectionThe three operating modes of the TDA7492MV are set by the two inputs STBY(pin 20)and

45、MUTE(pin 21).?Standby mode:all circuits are turned off,very low current consumption.?Mute mode:inputs are connected to ground and the positive and negative PWM outputs are at 50%duty cycle.?Play mode:the amplifiers are active.The protection functions of the TDA7492MV are realized by pulling down the

46、 voltages of the STBY and MUTE inputs shown in Figure 22.The input current of the corresponding pins must be limited to 200 A.Figure 22.Standby and mute circuits Figure 23.Turn-on/off sequence for minimizing speaker“pop”Table 7.Mode settingsMode SelectionSTBY MUTEStandbyL(1)1.Drive levels defined in

47、 Table 5:Electrical specifications on page 8X(dont care)MuteH(1)LPlayHHSTBYMUTE0 V3.3 VC72.2 FR230 kStandby0 V3.3 VC152.2 FR430 kMuteTDA7492MVTDA7492MVApplications informationDoc ID 16264 Rev 121/26 6.3 Gain settingThe gain of the TDA7492MV is set by the two inputs,GAIN0(pin 30)and GAIN1(pin 31).Int

48、ernally,the gain is set by changing the feedback resistors of the amplifier.6.4 Input resistance and capacitanceThe input impedance is set by an internal resistor Ri=60 k(typical).An input capacitor(Ci)is required to couple the AC input signal.The equivalent circuit and frequency response of the inp

49、ut components are shown in Figure 24.For Ci=470 nF the high-pass filter cut-off frequency is below 20 Hz:fc=1/(2*Ri*Ci)Figure 24.Device input circuit and frequency response Table 8.Gain settingsGAIN0GAIN1Nominal gain,Gv(dB)LL21.6LH27.6HL31.1HH33.6RiInputCiRfInputpinsignal Applications informationTDA

50、7492MV22/26 Doc ID 16264 Rev 16.5 Internal and external clocks The clock of the class-D amplifier can be generated internally or can be driven by an external source.If two or more class-D amplifiers are used in the same system,it is recommended that all devices operate at the same clock frequency.Th