数字电路英文版第八单元学习教案.pptx
《数字电路英文版第八单元学习教案.pptx》由会员分享,可在线阅读,更多相关《数字电路英文版第八单元学习教案.pptx(123页珍藏版)》请在淘文阁 - 分享文档赚钱的网站上搜索。
1、会计学1数字电路英文版第八数字电路英文版第八(d b)单元单元第一页,共123页。Monostable (单稳态单稳态)One-shot (单稳单稳)Preset (预置预置1)RESET (置置0)SET (置置1)Set-up time (设置时间设置时间(shjin)S-R flip-flop(RS触发器触发器)Synchronous (同步同步)Timer (计时器计时器)Toggle (触发触发,计数计数)第2页/共123页第二页,共123页。KEY TERMS n nAstable Having no stable state.An astable multivibrator os
2、cillates between two quasistable states.n nAsynchronous Having no fixed time relationship.n nBistable Having two stable states.Flip-flops and latches are bistable multivibrators.第3页/共123页第三页,共123页。n nClear An asynchronous input used to reset a flip-flop(make the Q output 0).n nD flip-flop A type of
3、bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.第4页/共123页第四页,共123页。n nEdge-triggered flip-flop A type of flip-flop in which the data are entered and appear on the output on the same clock edge.n nFeedback The output voltage or a por
4、tion of it that is connected back to the input of a circuit.第5页/共123页第五页,共123页。n nHold time The time interval required for the control levels to remain on the inputs to a flip-flop after the triggering edge of the clock in order to reliably activate the device.n nLatch A bistable digital circuit use
5、d for storing a bit.第6页/共123页第六页,共123页。n nHystersis A characteristic of a threshold-triggered circuit,such as the Schmitt trigger,where the device turns on and off at different input levels.n nJ-K flip-flop A type of flip-flop that can operate in the SET,RESET,no-change,and toggle modes.第7页/共123页第七页
6、,共123页。n nMaster-slave flip-flop A type of flip-flop in which the input data are entered into the device on the leading edges of clock pulses and apper at the output on trailing edges.Master-slave flip-flops have,for the most part,been replaced by edge-triggered types.第8页/共123页第八页,共123页。n nMonostabl
7、e Having only one stable state.A monostable multivibrator,commonly called a one-shot,produces a single pulse in response to a triggering input.n nOne-shot A monostable multivibrator.n nPreset An asynchronous input used to set a flip-flop(make the Q output 1).第9页/共123页第九页,共123页。n nRESET The state of
8、a flip-flop or latch when the output is 0;the action of producing a RESET state.n nSET The state of a flip-flop or latch when the output is 1;the action of producing a SET state.第10页/共123页第十页,共123页。n nSet-up time The time interval required for the control levels to be on the inputs to a digital circ
9、uit,such as a flip-flop,prior to the triggering edge of a clock pulse.n nS-R flip-flop A SET-RESET flip-flop.第11页/共123页第十一页,共123页。n nSynchronous Having a fixed time relationship.n nToggle The action of a flip-flop when it changes state on each clock pulse.第12页/共123页第十二页,共123页。8.1 LATCHES 8.1 LATCHES
10、The latch is a type of temporary storage device that has two stable states (bistable)and is normally placed in a category separate from that of flip-flop.2.第13页/共123页第十三页,共123页。Latches are basically similar to flip-flops because they are bistable devices that can reside in either of two states using
11、 a feedback arrangement,in which the outputs are connected back to the opposite inputs.The main difference between latches and flip-flop is in the method used for changing their state.3.第14页/共123页第十四页,共123页。The S-R(SET-RESET)LatchRSQQ(a)Active-HIGH input S-R latch (NOR S-R Latch)4.第15页/共123页第十五页,共12
12、3页。QQSR5VRRRRRR5.第16页/共123页第十六页,共123页。SRQQ(b)Active-LOW input S-R latch (NAND S-R Latch)6.第17页/共123页第十七页,共123页。SRQQWhen Q is HIGH,Q is LOW,and when Q is LOW,Q is HIGH.7.第18页/共123页第十八页,共123页。第19页/共123页第十九页,共123页。第20页/共123页第二十页,共123页。Input Outputs S R Q Q Comments 1 1 NC NC No change.latch remains in
13、present state.0 1 1 0 Latch SET.1 0 0 1 Latch RESET.0 0 1 1 Invalid condition.TABLE 8-1Truth table for an active-LOW input S-R latch.8.第21页/共123页第二十一页,共123页。Input Outputs S R Q Q Comments 0 0 NC NC No change.latch remains in present state.0 1 0 1 Latch RESET.1 0 1 0 Latch SET.1 1 0 0 Invalid conditi
14、on.TABLE 8-1Truth table for an active-HIGH input S-R latch.第22页/共123页第二十二页,共123页。SRQQ(a)Active-HIGH input S-R latchSRQQ(b)Active-LOW input S-R latchSR9.第23页/共123页第二十三页,共123页。EXAMPLE 8-1SRQ10.第24页/共123页第二十四页,共123页。EXAMPLE 8-1:Related Problem Determine the Q output of an active-HIGH input S-R latch if
15、 the waveforms in above are inverted and applied to the input.SRQ第25页/共123页第二十五页,共123页。Although S remains LOW for only a very short time before the switch bounce,this is sufficient to set the latch.第26页/共123页第二十六页,共123页。The Gated S-R LatchSRQQENSREN(a)Logic diagram(b)Logic symbol12.The latch will no
16、t change until EN is HIGH,but as long as it remains HIGH,the output is controlled by the state of the S and R inputs.第27页/共123页第二十七页,共123页。EXAMPLE 8-2 Determine the output waveform if the inputs shown in Fig.8-9 are applied to a gated S-R latch that is initially RESET.SRQEN13.Fig.8-9(a)(b)第28页/共123页
17、第二十八页,共123页。EXAMPLE 8-2:Related Problem Determine the Q output of a gated S-R latch if the S and R inputs in Fig.8-9(a)are inverted.SRQEN13.Fig.8-9(a)(b)第29页/共123页第二十九页,共123页。The Gated D LatchDQQENDEN(a)Logic diagram(b)Logic symbol14.QQQn+1=D(S)(R)第30页/共123页第三十页,共123页。EXAMPLE 8-3 Determine the Q out
18、put waveform if the inputs shown in Fig.8-11(a)are applied to a gated D latch,which is initially RESET.DQEN15.Fig.8-11(a)第31页/共123页第三十一页,共123页。EXAMPLE 8-3 Related Problem Determine the Q output of the gated D latch,if the D input in Fig.8-11(a)is reverted.DQEN(a)第32页/共123页第三十二页,共123页。Input Outputs D
19、 EN Q Q Comments 0 1 0 1 RESET.1 1 1 0 SET.X 0 Q0 Q0 No changeTruth table16.Qn+1=D第33页/共123页第三十三页,共123页。8.2 EDGE-TRIGGERED 8.2 EDGE-TRIGGERED FLIP-FLOPSFLIP-FLOPSFlip-flops are synchronous bistable devices,also known as bistable multivibrators.In this case,the term synchronous means that the output
20、changes state only at a specified point on a triggering input called the clock(CLK)which is designated as a control input C;that is,changes in the output occur in synchronization with the clock.17.第34页/共123页第三十四页,共123页。Edge-triggered flip-flop:SRQQCDQQCJKQQCSRQQCDQQCJKQQCTop:positive edge-triggered;
21、bottom:negative edge-triggered.18.第35页/共123页第三十五页,共123页。The Edge-Triggered S-R Flip-Flop:SRQQC Inputs Outputs 0 0 X Q0 Q0 No change S R CLK Q Q Comments 0 1 0 1 RESET 1 0 1 0 SET 1 1?Invalid19.Qn+1=S+RQn (SR=0 condition)第36页/共123页第三十六页,共123页。EXAMPLE 8-4SRQQC123456SRQCLK20.第37页/共123页第三十七页,共123页。EXAMP
22、LE 8-4 Determine Q for the S and R inputs in Fig.8-16(a)if the flip-flop is a negative edge-triggered device.123456SRQCLK第38页/共123页第三十八页,共123页。第39页/共123页第三十九页,共123页。PulsetransitiondetectorQQSRCLK01HIGH(1)LOW(0)01010101This gate is disabledBecause R is LOW.This gate is enabled.G4G3G2G1HIGHFig.8-1821.
23、第40页/共123页第四十页,共123页。PulsetransitiondetectorQQSRCLK01HIGH(1)LOW(0)01010101This gate is disabledbecause S is LOW.This gate is enabled.G4G3G2G1HIGHFig.8-1922.第41页/共123页第四十一页,共123页。The Edge-Triggered D Flip-Flop:SQQCDCLK Inputs Outputs 1 1 0 SET(1)D CLK Q Q Comments 0 0 1 RESET(0)23.R第42页/共123页第四十二页,共1
24、23页。EXAMPLE 8-5DQQC1234QDCLK24.第43页/共123页第四十三页,共123页。1234QDCLKEXAMPLE 8-5 Related Problem Determine the Q output for the D flip-flop if the D input in Fig.8-21(a)is reversed.第44页/共123页第四十四页,共123页。1234QDCLKEXAMPLE 8-5 Related Problem Determine the Q output for the D flip-flop if the D input in Fig.8-
25、21(a)is reversed.第45页/共123页第四十五页,共123页。The Edge-Triggered J-K Flip-Flop:JKQQC Inputs Outputs 0 0 Q0 Q0 No change J K CLK Q Q Comments 0 1 0 1 RESET 1 0 1 0 SET 1 1 Q0 Q0 Toggle25.Qn+1=J Qn+KQn第46页/共123页第四十六页,共123页。Inputs Output 0 0 0 0 J K Qn Qn+1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 数字电路 英文 第八 单元 学习 教案
限制150内