数字电路英文版第九单元学习教案.pptx

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1、数字电路英文版第九单元数字电路英文版第九单元(dnyun)第一页，共123页。Asynchronouscounter(异步计数器)Cascade(串级)Decade(十进制)Decadecounter(十进制计数器)Recycle(循环)Ripplecounter(纹波计数器)Sequence(时序)Sequentialcircuit(时序电路)Statediagram(状态图)Statemachine(状态机)Synchronouscounter(同步计数器)Truncated(截断(jidun)Truncatedsequence(无关态)Up/Downcounter(加减计数器)第1页/共

2、123页第二页，共123页。KEY TERMSAsynchronous counter A type of counter in which each stage is clocked from the output of the preceding stage.Cascade To connect“end-to-end”as when several counters are connected from the terminal count output of one counter to the enable input of the next counter.第2页/共123页第三页，

3、共123页。Decade Characterized by ten states or values.Decade counter A digital counter having ten states.Recycle To undergo transition from the final or terminal state back to the initial state.Ripple counter An asynchronous counter.第3页/共123页第四页，共123页。Sequence The order in which several things occur in

4、 a specified time relationship.Sequential circuit A digital circuit whose logic states follow on a specified time sequence.State diagram A graphic depicition of a sequence of states or values.第4页/共123页第五页，共123页。State machine A logic system exhibiting a sequence of states conditioned by internal logi

5、c and external inputs;any sequential circuit exhibiting a specified sequence of states.Terminal count The final state in a counters sequence.第5页/共123页第六页，共123页。Synchronous counter A type of counter in which each stage is clocked by the same pulse.Truncated Shortened.Truncated sequence A sequence tha

6、t does not include all of the possible states of a counter.第6页/共123页第七页，共123页。Up/Down counter A counter that can progress in either direction through a certain sequence.第7页/共123页第八页，共123页。9.1 ASYNCHRONOUS COUNTER OPERATIONThetermasynchronousreferstoeventsthatdonothaveafixedtimerelationshipwitheachot

7、herand,generally,donotoccuratthesametime.AnasynchronouscounterisoneinwhichtheFFwithinthecounterdonotchangestatesatexactlythesametimebecausetheydonothaveacommonclockpulse.2.第8页/共123页第九页，共123页。A 2-Bit Asynchronous Binary CounterJ0K0Q0CHIGHCLK2134Q0J1K1Q1CQ1Q0CLKQ03.第9页/共123页第十页，共123页。ClockPulseQ1Q0Ini

8、tially00101210311400BinarystatesequenceforthecounterinFigureabove.4.第10页/共123页第十一页，共123页。A 2-Bit Asynchronous Binary CounterJ0K0Q0CHIGHCLK2134Q0J1K1Q1CQ1CLKQ0第11页/共123页第十二页，共123页。A 2-Bit Asynchronous Binary CounterJ0K0Q0CHIGHCLK2134Q0J1K1Q1CQ1CLKQ0第12页/共123页第十三页，共123页。ClockPulseQ1Q0Initially00111210

9、301400BinarystatesequenceforthecounterinFigureabove.第13页/共123页第十四页，共123页。A 3-Bit Asynchronous Binary CounterClockPulseQ2Q1Q0Initially0001001201030114100Binary state sequence for a 3-bit binary counter.5101611071118(recycle)0005.第14页/共123页第十五页，共123页。J0K0Q0CJ1K1Q1CQ0HIGHJ2K2Q2CQ1FF2FF1FF01CLKQ0Q1Q2111

10、1011111110000000000000012345678CLK6.第15页/共123页第十六页，共123页。J0K0Q0CJ1K1Q1CJ2K2CFF2FF1FF0EXAMPLE9-1Afour-bitasynchronousbinarycounterisshowninasfollow:Q2J3K3CQ3FF3CLKHIGH第16页/共123页第十七页，共123页。CLKQ0Q1Q21234Q3111000000000000110010100110001111111001056789101112131415161010101111000011110011001100第17页/共123页第

11、十八页，共123页。J0K0Q0CJ1K1Q1CCLRJ2K2CFF2FF1FF0AsynchronousDecadeCounterQ2J3K3CQ3FF3CLR10decoderCLKHIGH7.第18页/共123页第十九页，共123页。CLKQ0Q1Q212345678910Q3CLRGlitchGlitch8.1110000000000001100101001100010111010010第19页/共123页第二十页，共123页。EXAMPLE9-2Showhowanasynchronouscountercanbeimplementedhavingamodulusoftwelvewith

12、astraightbinarysequencefrom0000through1011.Q3Q2Q1Q0000010111100RecycleNormalnextstate第20页/共123页第二十一页，共123页。J0K0Q0CJ1K1Q1CJ2K2CFF2FF1FF0Q2J3K3CQ3FF3CLR12decoderCLKHIGH第21页/共123页第二十二页，共123页。J0K0Q0CJ1K1Q1CJ2K2CFF2FF1FF0Q2J3K3CQ3FF3CLR13decoderCLKHIGHRelatedproblem:EXAMPLE9-2第22页/共123页第二十三页，共123页。A4-Bit

13、AsynchronousBinaryCounterJ0K0Q0CJ1K1Q1CJ2K2CFF2FF1FF0Q2J3K3CQ3FF3CLRCLKB(1)CLKA(14)RO(1)RO(2)(2)(3)(12)(9)(8)(11)9.第23页/共123页第二十四页，共123页。CCCTRDIV16CLKACLKBRO(1)RO(2)Q3Q2Q1Q0(a)74LS93Aconnectedasamodulus-16counter10.第24页/共123页第二十五页，共123页。CCCTRDIV10CLKACLKBRO(1)RO(2)Q3Q2Q1Q0(b)74LS93Aconnectedasadecad

14、ecounter11.第25页/共123页第二十六页，共123页。EXAMPLE9-3Showhowthe74LS93Acanbeusedasamodulus12counter.CCCTRDIV10CLKACLKBRO(1)RO(2)Q3Q2Q1Q012.第26页/共123页第二十七页，共123页。Related Problem:modulus-13 counterCC74LS93ACLKACLKBRO(1)RO(2)Q3Q2Q1Q013.第27页/共123页第二十八页，共123页。9.2 SYNCHRONOUS COUNTER OPERATIONThetermsynchronousrefer

15、stoeventsthathaveafixedtimerelationshipwitheachother.WithrespecttocounteroperationsynchronousmeansthatalltheFFinthecounterareclockedatthesametimebyacommonclockpulse.14.第28页/共123页第二十九页，共123页。A 2-Bit Synchronous Binary CounterJ0K0Q0CHIGHCLK2134Q0J1K1Q1CQ1CLKQ115.第29页/共123页第三十页，共123页。A 3-Bit Synchronou

16、s Binary CounterJ0K0Q0CJ1K1Q1CQ0HIGHJ2K2CQ1FF2FF1FF0Q2CLK16.第30页/共123页第三十一页，共123页。1CLKQ0Q1Q2111101111111000000000000001234567817.第31页/共123页第三十二页，共123页。ClockPulseQ2Q1Q0Initially0001001201030114100Binary state sequence for a 3-bit binary counter.5101611071118(recycle)00018.第32页/共123页第三十三页，共123页。J0K0Q0

17、CJ1K1Q1CJ2K2CFF2FF1FF0SynchronousBinaryCounterQ2J3K3CQ3FF3CLKHIGHQ0Q1Q2Q0Q119.第33页/共123页第三十四页，共123页。CLKQ1Q2Q3Q0Q0Q1Q0Q1Q0Q1Q2Q0Q1Q220.第34页/共123页第三十五页，共123页。A4-BitSynchronousDecadeCounterJ0K0Q0CJ1K1Q1CJ2K2CFF2FF1FF0Q2J3K3CQ3FF3HIGHCLKQ321.第35页/共123页第三十六页，共123页。CLKQ0Q1Q212345678910Q322.第36页/共123页第三十七页

18、，共123页。ClockPulseQ3Q2Q1Q0Initially000010001200103001140100States of a BCD decade counter50101601107011110(recycles)0000910018100023.第37页/共123页第三十八页，共123页。J0=K0=1,J1=K1=Q0Q3J2=K2=Q0Q1,J3=K3=Q0Q1Q2+Q0Q324.第38页/共123页第三十九页，共123页。9.3 UP/DOWN SYNCHRONOUS COUNTERSAnup/downcounterisonethatiscapableofprogres

19、singineitherdirectionthroughacertainsequence.Anup/downcounter,sometimescalledabidirectionalcounter,canhaveanyspecifiedsequenceofstates.25.第39页/共123页第四十页，共123页。A3-bitbinarycounterthatadvancesupwardthroughitssequence(0,1,2,3,4,5,6,7)andthencanbereversedsothatitgoesthroughthesequenceintheoppositedirect

20、ion(7,6,5,4,3,2,1,0)isanillustrationofup/downsequentialoperation.0,1,2,3,4,5,4,3,2,3,4,5,6,7,6,5,ect.DOWNDOWNUPUP26.第40页/共123页第四十一页，共123页。ClockPulseUPQ2Q1Q0DOWN0000Up/Down sequence for a 3-bit counter.100120103011410051016110711127.第41页/共123页第四十二页，共123页。J0=K0=1J1=K1=(Q0*UP)+(Q0*DOWN)J2=K2=(Q0*Q1*UP)

21、+(Q0*Q1*DOWN)28.第42页/共123页第四十三页，共123页。J0K0CJ1K1CJ2K2CQ0FF0HIGHFF1FF2Q0Q1Q1Q2Q2CLKU/DDOWNUPQ0*UPQ0*DOWN29.第43页/共123页第四十四页，共123页。EXAMPLE9-4Showthetimingdiagramanddeterminethesequenceofa4-bitsynchronousbinaryup/downcounteriftheclockandUP/DOWNcontrolinputshavewaveformsasshowninFig.9-24(a).Thecounterstar

22、tsintheall0sstateandispositiveedge-triggered.第44页/共123页第四十五页，共123页。CLKQ1Q2Q3Q0UPDOWNDOWNUPUP/DOWN30.10000011001000001010000010111000100000011011100000000000Fig.9-24(a)第45页/共123页第四十六页，共123页。Q3Q2Q1Q0000000010010001101000011001000010000111100000001001000010000UPUPDOWNDOWN31.第46页/共123页第四十七页，共123页。Relate

23、dProblemShowthetimingdiagramiftheUP/DOWNcontrolwaveforminFigure9-24(a)isinverted.第47页/共123页第四十八页，共123页。CLKQ1Q2Q3Q0UPDOWNDOWNUPUP/DOWN30.11110111101010011011111110111010100000011011101100111000Fig.9-24(a)0000第48页/共123页第四十九页，共123页。9.4 DESIGN OF SYNCHRONOUS COUNTERThissectionisrecommendedforthosewhowan

24、tanintroductiontocounterdesignortostatemachinedesigningeneral.32.第49页/共123页第五十页，共123页。GeneralModelofaSequentialCircuitCombinationallogicMemoryI0I1ImY0Y1YpQ0Q1QnQ0Q1QxCLKExcitationlinesStatevariablelines33.第50页/共123页第五十一页，共123页。Step1:StateDiagram000110011101001010100111Statediagramfora3-bitGraycodeco

25、unter.34.第51页/共123页第五十二页，共123页。Step2:Next-StateTableQ2Q1Q0Q2Q1Q0PresentStateNextState000001001011011010010110110111111101101100100000Next-statetablefor3-bitGraycodecounter.35.第52页/共123页第五十三页，共123页。Step3:Flip-FlopTransitionTableQNQN+1JKOutputTransitionFlip-FlopInput000XTransitiontableforaJ-Kflip-flop

26、.011X10X111X036.第53页/共123页第五十四页，共123页。Step4:K-MAPPresentStateNextStateQ2Q1Q0Q2Q1Q0100000001011011010010110110111111101OutputFlip-flopTransitionsInputsQNQN+1JK000X11X00001111001Q2Q1Q0K0map0001111001Q2Q1Q0J0map00000110110010X1011X1X1X37.第54页/共123页第五十五页，共123页。0001111001Q2Q1Q01X0001111001Q2Q1Q0100001111

27、001Q2Q1Q01X0001111001Q2Q1Q01X0001111001Q2Q1Q0X0001111001Q2Q1Q01X00XXXXXXX0001XXX000000XXXXXXXXX100001Q1Q0Q2Q0Q1Q0Q2Q1Q2Q1Q2Q1Q2Q1Q2Q1J2mapJ1mapJ0mapK2mapK1mapK0map38.第55页/共123页第五十六页，共123页。Step5:LogicExpressionforFlip-FlopInputJ0=Q2Q1+Q2Q1=Q2+Q1K0=Q2Q1+Q2Q1=Q2+Q1J1=Q2Q0K1=Q2Q0J2=Q1Q0K2=Q1Q039.第56页/共1

28、23页第五十七页，共123页。J0K0CJ1K1CJ2K2CQ0FF0FF1FF2Q0Q1CLKQ2Q2Q140.第57页/共123页第五十八页，共123页。To design in another way000111100111010001Q2Q1Q2Q1Q0mapQ2Q1Q0Q0n+1=Q2Q1+Q2Q1=Q2+Q1(Q0+Q0)=Q2+Q1Q0+Q2+Q1Q0J0=Q2+Q1K0=Q2+Q1Qn+1=JQn+KQn第58页/共123页第五十九页，共123页。0001111001Q2Q1Q011000110Q2Q0Q1mapQ1Q0Q1n+1=Q1Q0+Q2Q0(Q1+Q1)=Q0Q1+Q

29、2Q0Q1+Q2Q0Q1=(Q0+Q2Q0)Q1+Q2Q0Q1=Q2Q0Q1+Q2Q0Q1J1=Q2Q0K1=Q2Q0Qn+1=JQn+KQn第59页/共123页第六十页，共123页。0001111001Q2Q1Q010001101Q1Q0Q2mapQ0Q2Q2n+1=Q1Q0+Q0Q2=Q1Q0(Q2+Q2)+Q0Q2=(Q0+Q1Q0)Q2+Q1Q0Q2=Q1Q0Q2+Q1Q0Q2J2=Q1Q0K2=Q1Q0Qn+1=JQn+KQn第60页/共123页第六十一页，共123页。EXAMPLE9-5:UseJ-KFF001101010111PresentStateNextState001010

30、Q2Q1Q0Q2Q1Q001010110111111100141.第61页/共123页第六十二页，共123页。QNQN+1JKOutputTransitionFlip-FlopInput000XTransitiontableforaJ-Kflip-flop.011X10X111X042.第62页/共123页第六十三页，共123页。0001111001Q2Q1Q0XX0001111001Q2Q1Q0100001111001Q2Q1Q01X0001111001Q2Q1Q0XX0001111001Q2Q1Q0X0001111001Q2Q1Q01XXXXXXXXXXX10XXXX1XXX1XXXXXX

31、XXXX0101XXQ11Q11Q21J2mapJ1mapJ0mapK2mapK1mapK0map43.第63页/共123页第六十四页，共123页。J0K0CCLKJ1K1CQ0J2K2CQ2Q1Q211J0=1,K0=Q2J1=K1=1J2=K2=Q144.第64页/共123页第六十五页，共123页。To design in another way0001111001X0X111XXQ0Q2Q0Q0mapQ2Q1Q0Q0n+1=Q0+Q2Q0J0=1K0=Q2Qn+1=JQn+KQn第65页/共123页第六十六页，共123页。0001111001X0X110XXQ1Q1mapQ2Q1Q0Q1

32、n+1=Q1J1=1K1=1Qn+1=JQn+KQn第66页/共123页第六十七页，共123页。0001111001X0X101XXQ2Q1Q2mapQ2Q1Q0Q2n+1=Q1Q2+Q1Q2J2=K2=Q1Qn+1=JQn+KQnQ2Q1第67页/共123页第六十八页，共123页。9.5 CASCADED COUNTERSCounterscanbeconnectedincascadetoachievehigher-modulusoperation.Inessence,cascadingmeansthatthelast-stageoutputofonecounterdrivestheinput

33、ofthenextcounter.45.第68页/共123页第六十九页，共123页。J0K0CCLKJ1K1CJ2K2CJ3K3CJ4K4CQ4Q0Q1Q2Q3Modulus-4counterModulus-8counterTwocascadedcounters(allJandKareHIGH).46.第69页/共123页第七十页，共123页。CTRDIV10CTENQ0Q1Q2Q3TCCCOUNTER1CTRDIV10CTENQ0Q1Q2Q3TCCCOUNTER2HIGHCLKfinfinfin10100Amodulus-100counterusingtwocascadecounters.4

34、7.第70页/共123页第七十一页，共123页。CTRDIV10CTENTCCHIGHCTRDIV10CTENTCCCTRDIV10CTENTCC100kHz10kHz1kHz1MHz48.第71页/共123页第七十二页，共123页。CTRDIV16ENPD3D2D1D0RCOC0000ENTCTRDIV16ENPD3D2D1D0RCOCENTCTRDIV16ENPD3D2D1D0RCOCENTCTRDIV16ENPD3D2D1D0RCOCENT110000110110016C16316616CLKLOADMSDLSDOutput49.第72页/共123页第七十三页，共123页。216=65,

35、536(63C0)16=6*163+3*162+12*16=25,53665,53625,536=40,00050.第73页/共123页第七十四页，共123页。9.6 COUNTER DECODINGInmanyapplications,itisnecessarythatsomeorallofthecounterstatesbedecoded.Thedecodingofacounterinvolvesusingdecodersorlogicgatestodeterminewhenthecounterisinacertainbinarystateinitssequence.Forinstance

36、,theterminalcountfunctionpreviouslydiscussedisasingledecodedstateinthecountersequence.51.第74页/共123页第七十五页，共123页。J0K0CJ1K1CJ2K2CQ0Q0Q1Q2CLKHIGHLSBMSBDecoded6Q0Q2Q111152.第75页/共123页第七十六页，共123页。EXAMPLE9-9Decoding2and7J0K0CJ1K1CJ2K2CQ0Q0Q1Q2LSBMSBFF0FF1FF2CLK12753.第76页/共123页第七十七页，共123页。1CLKQ0Q1Q2111101111

37、111000000000000001234567827Decodedoutput54.第77页/共123页第七十八页，共123页。A3-bitUp/DownGrayCodeCounterDesign000110011101001010100111Statediagramfora3-bitGraycodecounter.Y=1Y=055.第78页/共123页第七十九页，共123页。Q2Q1Q0Q2Q1Q0Q2Q1Q0PresentStateNextState000100001Y=0(DOWN)Y=1(UP)001000011011001010010011110110010111111110101

38、10111110010010100056.第79页/共123页第八十页，共123页。QNQN+1JKOutputTransitionFlip-FlopInput000XTransitiontableforaJ-Kflip-flop.011X10X111X0第80页/共123页第八十一页，共123页。Q2Q1Q0YQ2Q1Q0Y01X11X1111XX00000000010101011111111110101010K0mapJ0mapQ2Q1YQ2Q1YQ2Q1YQ2Q1YQ2Q1YQ2Q1YQ2Q1YQ0YXXXX000X1X1XXXXX0000Q2Q1Y第81页/共123页第八十二页，共12

39、3页。Q2Q1Q0YQ2Q1Q0YXXX000XXX0X000000000010101011111111110101010K1mapJ1mapQ2Q0YQ2Q1YQ2Q0YQ2Q0YQ0Y1XX00X0X01XX000XX11X第82页/共123页第八十三页，共123页。Q2Q1Q0YQ2Q1Q0Y1XX0X0X0001100000000010101011111111110101010K2mapJ2mapQ1Q0YQ1Q0YQ1Q0YQ1Q0YQ0Y00XXXX0XXXXXX00X0X01第83页/共123页第八十四页，共123页。QNQN+1DOutputTransitionFlip-Flo

40、pInput000TransitiontableforaDflip-flop.01110011157.第84页/共123页第八十五页，共123页。Q2Q1Q0YQ2Q1Q0Y111111111111111100000000010101011111111110101010D0mapD1mapQ2Q1YQ2Q1YQ2Q1YQ2Q1YQ2Q0YQ1Q0Q2Q0YQ0Y58.第85页/共123页第八十六页，共123页。Q2Q111111110000010111111010D2mapQ1Q0YQ2Q0Q1Q0Y1Q0Y59.第86页/共123页第八十七页，共123页。TheBooleanExpressi

41、onsfortheDInputsD0=Q2Q1Y+Q2Q1Y+Q2Q1Y+Q2Q1YD1=Q2Q0Y+Q2Q0Y+Q1Q0D2=Q1Q0Y+Q1Q0Y+Q2Q0Logicdiagramofthe3-bitup/downGraycodecounterinpage584Figure11-13.60.第87页/共123页第八十八页，共123页。Design problem 2-sequence detector Consider a synchronous sequential logic circuit that will detect a defined serial pattern appea

42、ring on a signal data input.Suppose the serial input to detect is 0110011,with Z becoming a 1 immediately after the last bit appears in the sequence.第88页/共123页第八十九页，共123页。Design procedure1.Derive the state diagram.2.Draw the state table.3.Assign state variable patterns to states.4.Draw the assigned

43、state table.5.Derive the flip-flop input functions,and in our design.6.Derive the output function of a K-map,and finally.7.Draw the logic circuit.第89页/共123页第九十页，共123页。1/02/03/04/05/06/07/08/10110010010001111Statediagram0110011StatenumberOutputZ第90页/共123页第九十一页，共123页。1/02/03/04/05/06/07/08/10110010010

44、00111Statediagram0110110011StatenumberOutputZ第91页/共123页第九十二页，共123页。State table present state Next state output x=0 x=1 Z 1 2 1 0 1 2 1 0 2 2 3 0 2 2 3 0 3 2 4 0 3 2 4 0 4 5 1 0 4 5 1 0 5 6 5 6 3 3 0 0 6 2 7 0 6 2 7 0 7 2 8 0 7 2 8 0 8 2 1 1 8 2 1 1第92页/共123页第九十三页，共123页。State variable assignmentFor e

45、xample:state 1=001,state 2=010,state 3=011,state 4=100,state 5=101,state 6=110,state 7=111,state 8=000.There are a very large number of possible assignments and each would lead to specific next state and output functions.第93页/共123页第九十四页，共123页。Rule 1 Assign codes which differ in one variable to state

46、s that lead to the same next state.(次态相同次态相同,现态应相邻现态应相邻(xin ln)编码编码)001011000第94页/共123页第九十五页，共123页。Rule 2 Assign codes that differ in one variable for next states of a present state.(现态相同现态相同,次态应相邻次态应相邻(xin ln)编码编码)100000110第95页/共123页第九十六页，共123页。We make the assignment:state 1=000,state 2=111,state 3

47、=101,state 4=001,state 5=010,state 6=110,state 7=011,state 8=100第96页/共123页第九十七页，共123页。present state Next state output y3y2y1 x=0 x=1 Z 000 111 000 000 111 000 0 0 111 111 101 111 111 101 0 0 101 111 001 0 101 111 001 0 001 010 000 0 001 010 000 0 010 110 010 110 101101 0 0 110 111 011 110 111 011 0

48、0 011 111 100 0 011 111 100 0 100 111 000 1 100 111 000 1 第97页/共123页第九十八页，共123页。Flip-flop input functions The input functions for the three flip-flops are obtained as before by mapping the next state variables in the assigned state table onto Karnaugh maps.第98页/共123页第九十九页，共123页。xy3xy3Q0Y111111111111

49、00000000010101011111111110101010 xy3y2y1y2y1xy1xy3y2y1y2y1111111Y3Y21y3y2第99页/共123页第一百页，共123页。xy3Q0Y11110000010111111010 xy2y1y3y1y2y1111Y11y3y2y1xy2y1Y3=xy1+xy3+y2y1+y3y2Y2=x+y3y2y1Y1=y3y1+y3y2y1+xy2y1+xy2y1+xy2y1OutputfunctionZ=y3y2y1Drawlogiccircuit.11xy2y1第100页/共123页第一百零一页，共123页。Mealymodeldesign

50、sThe Mealy model state diagram indicates the outputs on the arcs leading to the state,together with the inputs that caused the transition to that state.Often the Mealy model state diagram has less states than a Moore model state diagram for the same problem.第101页/共123页第一百零二页，共123页。The same design st