基于51单片机的电子数字钟设计的外文翻译.pdf
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1、文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.基于 51 单片机的电子数字钟设计的外文翻译 AT89C51 Family Users Guide 1 Features Compatible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance 1000 WriteErase Cycles Fully Static Operation 0 Hz to 24 MHz Three-level Program Memory Lock 128 x 8-bit Internal R
2、AM 32 Programmable IO Lines Two 16-bit TimerCounters Six Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down Modes 2 Description The AT89C51 is a low-power high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory PEROM The de
3、vice is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pin-out The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer By combining a vers
4、atile 8-bit CPU with Flash on a monolithic 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.chip the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications 3 Pin Configurations 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.4 Lock Diagram The AT8
5、9C51 provides the following standard features 4K bytes of Flash 128 bytes of RAM 32 IO lines two 16-bit timercounters a five vector two-level interrupt architecture a full duplex serial port on-chip oscillator and clock circuitry In addition the AT89C51 is designed with static logic for operation do
6、wn to zero frequency and supports two software selectable power saving modes The Idle Mode stops the CPU while allowing the RAM timercounters serial port and interrupt system to continue functioning The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functi
7、ons until the next hardware reset 5 Pin Description VCC Supply voltage GND Ground Port 0 Port 0 is an 8-bit open-drain bi-directional IO port As an output port each pin can sink eight TTL inputs When 1s are written to port 0 pins the pins can be used as high-impedance inputs Port 0 may also be confi
8、gured to be the multiplexed low-order addressdata bus during accesses to external program and data memory In this mode P0 has internal pull-ups Port 0 also receives the code bytes during Flash programming and 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.outputs the code bytes during program verification External
9、 pull-ups are required during program verification Port 1 Port 1 is an 8-bit bi-directional IO port with internal pull-ups The Port 1 output buffers can sinksource four TTL inputs When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs As inputs Por
10、t 1 pins that are externally being pulled low will source current IIL because of the internal pull-ups Port 1 also receives the low-order address bytes during Flash programming and verification Port 2 Port 2 is an 8-bit bi-directional IO port with internal pull-ups The Port 2 output buffers can sink
11、source four TTL inputs When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current IIL because of the internal pull-ups Port 2 emits the high-order address byte during fetche
12、s from external program memory and during accesses to external data memory that uses 16-bit addresses MOVX DPTR In this application it uses strong internal pull-ups when emitting 1s During accesses to external data memory that uses 8-bit addresses MOVX RI Port 2 emits the contents of the P2 Special
13、Function Register Port 2 also receives the high-order address bits and some control 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.signals during Flash programming and verification Port 3 Port 3 is an 8-bit bi-directional IO port with internal pull-ups The Port 3 output buffers can sinksource four TTL inputs When
14、1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs As inputs Port 3 pins that are externally being pulled low will source current IIL because of the pull-ups Port 3 also serves the functions of various special features of the AT89C51 as listed below
15、 Port Pin Alternate Functions P30 RXD serial input port P31 TXD serial output port P32 INT0 external interrupt 0 P33 INT1 external interrupt 1 P34 T0 timer 0 external input P35 T1 timer 1 external input P36 WR external data memory write strobe P37 RD external data memory read strobe Port 3 also rece
16、ives some control signals for Flash programming and verification RST Reset input A high on this pin for two machine cycles while the oscillator is running resets the device ALE Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory This pin is a
17、lso the program pulse input PROG during Flash programming In normal operation ALE is emitted at a constant rate of 16 the oscillator frequency and may be used 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to ext
18、ernal Data Memory If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With the bit set ALE is active only during a MOVX or MOVC instruction Otherwise the pin is weakly pulled high Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode
19、 Program Store Enable is the read strobe to external program memory When the AT89C51 is executing code from external program memory is activated twice each machine cycle except that two activations are skipped during each access to external data memory VPP External Access Enable must be strapped to
20、GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note however that if lock bit 1 is programmed will be internally latched on reset should be strapped to VC C for internal program executions This pin also receives the 12-volt program
21、ming enable voltage VPP during Flash programming for parts that require 12-volt VPP XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit XTAL2 Output from the inverting oscillator amplifier 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.6 Oscillator Characteristics XT
22、AL1 and XTAL2 are the input and output respectively of an inverting amplifier which can be configured for use as an on-chip oscillator as shown in Figure 1 Either a quartz crystal or ceramic resonator may be used To drive the device from an external clock source XTAL2 should be left unconnected whil
23、e XTAL1 is driven as shown in Figure 2 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and imum voltage high and low time specifications must be observed Oscillator Connection
24、s Note C1 C2 30 pF10 pF for Crystals40 pF10 pF for Ceramic ResonatorsExternal Clock Drive Configuration 7 Idle Mode In idle mode the CPU puts itself to sleep while all the on-chip peripherals remain active The mode is invoked by software The content of the on-chip RAM and all the special functions r
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