单片机外文翻译---AT89S52单片机-单片机.doc
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1、毕业设计外文翻译题 目 系 院 专 业 学生姓名 学 号 指导教师 职 称 2011年 6月 15日AT89S52The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the indus-t
2、ry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful micro
3、controller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-lev
4、el interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, time
5、r/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.VCC :Supply voltage.GND :Ground.Port 0:Port 0 is an 8-bit open drain bidirectio
6、nal I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0
7、 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.Port 1:Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers
8、can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be con
9、figured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table. Port 1 also receives the low-order address bytes during Flash programming and verification. Table1Port PinAlternate FunctionsT2 (externa
10、l count input to Timer/Counter 2), clock-outT2EX (Timer/Counter 2 capture/reload trigger and direction control)MOSI (used for In-System Programming)MISO (used for In-System Programming)SCK (used for In-System Programming)Port 2:Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Po
11、rt 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the
12、high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX R
13、I), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.Port 3:Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source f
14、our TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and
15、verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table.Table2Port PinAlternate FunctionsRXD (serial input port)TXD (serial output port) (external interrupt 0) (external interrupt 1)T0 (timer 0 external input)T1 (timer 1 external in
16、put) (external data memory write strobe) (external data memory read strobe)RST:Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8E
17、H) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/:Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input () during Flash p
18、rogramming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting
19、bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.:Program Store Enable () is the read strobe to external program
20、memory. When the AT89S52 is executing code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to exter-nal data memory./VPP:External Access Enable. must be strapped to GND in order to enable the device to fetch code from ex
21、ternal program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, will be internally latched on reset. should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming
22、.XTAL1:Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:Output from the inverting oscillator amplifier.3.Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data M
23、emory can be addressed.3.1 Program MemoryIf the pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to e
24、xternal memory.3.2 Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instr
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